Design of a 2.45 GHz RF-CMOS power splitter circuit for ISM RFID readers /
The recent demand for automatic radio frequency identification (RFID) tags, has triggered research for accompanying miniature, low-power reader circuits. Implementation of such circuits using conventional integrated fabrication techniques such as RF complementary metal-oxide-semiconductor (CMOS) is...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Gombak, Selangor :
Kulliyyah of Engineering, International Islamic University Malaysia,
2010
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| Subjects: | |
| Online Access: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
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| Summary: | The recent demand for automatic radio frequency identification (RFID) tags, has triggered research for accompanying miniature, low-power reader circuits. Implementation of such circuits using conventional integrated fabrication techniques such as RF complementary metal-oxide-semiconductor (CMOS) is desirable due to the low cost, reduction in parasitics and small-size. This research illustrates the design of a RF-CMOS power splitter for an RFID reader circuit to serve the ISM 2.45 GHz band. The power splitter design is based on a Wilkinson power splitter and utilizes spiral inductors, metal finger capacitors and high sheet poly resistors. The design utilizes the 0.18 2m Silterra RF-CMOS technology. Low return loss of 6.9 dB, low insertion loss 3 dB and high isolation 10dB were obtained from pre-layout simulations. The low insertion loss 1.496 dB was found from post-layout simulation. The overall power splitter circuit is simulated using AWR Microwave Office®, indicating its S-parameters. The individual inductors were designed using Sonnet® to obtain the appropriate inductance at 2.45 GHz. Further refinement of the inductor layout design was done using CST® to incorporate the effect of composite CMOS layers. Simulation results indicate that inductors core diameters must be adequately large (more than 100 2m) to ensure high quality factor characteristics and its conductor spacing should be minimal to obtain larger per unit area inductive value. Capacitor and resistor layout and extraction were performed using Cadence®. It shows the desired capacitance value of 1.39 pF required 101 fingers and the 2.2 pF required 105 fingers respectively. The high sheet poly resistor is used to implement the 300 Ohms resistor. The h-poly resistor had dimensions of 5.08 2m × 7.96 2m. Layout versus schematic simulations were performed using Cadence®. The floor plan for the power splitter was designed to fit two 1800 2m × 1800 2m chips. The post layout simulation results indicated satisfactory results which matched all the design requirements. |
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| Physical Description: | xvii, 103 leaves : ill. ; 30 cm. |
| Bibliography: | Includes bibliographical references (leaves 97-102). |