Single event psets on static random access memory by SPENVIS and PSPICE simulation at near equatorial orbits /
Memories, such as Static Random Access Memories (SRAMs) are important parts in microelectronic circuits. SRAM is used to store data in a circuit. In harsh space environments with high energetic radiation, SRAM devices are likely to interact with ionizing electrons, protons and various ions. This int...
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Main Author: | |
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Format: | Thesis |
Language: | English |
Published: |
Gombak, Selangor :
Kulliyyah of Engineering, International Islamic University Malaysia,
2016
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Subjects: | |
Online Access: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
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Summary: | Memories, such as Static Random Access Memories (SRAMs) are important parts in microelectronic circuits. SRAM is used to store data in a circuit. In harsh space environments with high energetic radiation, SRAM devices are likely to interact with ionizing electrons, protons and various ions. This interaction induces excess charge within the device that modifies its electronic state, causing various types of unwanted effects including Single Event Upset (SEU). This work computes the critical charge (Qcrit) that is required to upset 90nm and 180nm CMOS 6T SRAM cells at their two most sensitive nodes at Q and Qbar. Different current values are used with a supplied voltage ranging from 0.2 V to 1V. Based on the obtained critical charge, the single event upset rates are reported as a function of radiation particles, shielding and striking nodes (transistor drain) size. This investigation is performed by simulation devices in Near Equatorial Orbit (NEqO) environment, using ORCAD PSPICE and SPENVIS simulation tools. The results show that Q node is more vulnerable to SEU than Q bar node for both technologies similarly. 90nm SRAM is more susceptible to SEU than 180nm. It is also found that shielding by 0.5 mg/cm2 Al has no effect on Galactic Cosmic Rays(GCR) radiation. Solar particles (SP) dominates the effect rates, however trapped particles (TP) have the least effects. Drainlength plays an important role in the SEU rates variation. It may minimize the upset rates with small drain length and low supplied voltage. Shielding by 0.5 g/cm2 of Al and decreasing the drain length can mitigate the transistor susceptibility to SEU. Thus, it can be justified that smaller CMOS transistor technology has high potential to be used in space. |
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Item Description: | Abstracts in English and Arabic. "A dissertation submitted in fulfilment of the requirement for the degree of Master of Science (Electronics Engineering)." --On t.p. |
Physical Description: | xv, 92 leaves : ill. ; 30cm. |
Bibliography: | Includes bibliographical references (leaves 81-86). |