A new carbon nanotube model for high performance logic gates circuit /
Aggressive scaling of complementary metal oxide semiconductor (CMOS) has led to higher and higher integration density, the higher performance of devices, low power consumption and more complex function. However, it will eventually reach its limit to nanoscale size in near future. As device sizes app...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Kuala Lumpur :
Kulliyyah of Engineering, International Islamic University Malaysia,
2016
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| Subjects: | |
| Online Access: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
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| Summary: | Aggressive scaling of complementary metal oxide semiconductor (CMOS) has led to higher and higher integration density, the higher performance of devices, low power consumption and more complex function. However, it will eventually reach its limit to nanoscale size in near future. As device sizes approach the nanoscale, new opportunities arise from harnessing the physical properties at the nanoscale. Carbon Nanotubes are considered as the most promising carbon nanostructure material for nanoscale electronic device. In this research, a new model of carbon nanotube field-effect transistors (CNTFET) is proposed to design logic gate circuit. In this work, simulation approaches of tight binding method and density of states (DOS) of CNT have been developed and to explore device engineering issues for better transistor performance. By analyzing the electronic properties of CNT including energy dispersion relation, effective mass, doping, carrier concentration and temperature dependent bandgap, an optimum CNT has been considered in this research. An analytical current transport model has been developed to design a better performance CNTFET by analyzing charge, surface potential of the model. By using non equilibrium green function (NEGF) formulation, a better drain current has been achieved from the proposed CNTFET model. Finally a CNTFET model has been designed by using the analytical model parameter. From the details analysis of the device physics, CNT diameter is 1.95 nm and small band-gap is 0.44 eV have been achieved from the graphene's chirality of (25, 0). From analytical model, drain current 69 µA, sub threshold swing (SS) 68mV/decade and drain induced barrier lowering (DIBL) 53.19mV/decade have been found with the channel length of 14 nano meter (nm) CNTFET. Current gain 45 dB, frequency 10 THz have been achieved from the simulation of the model by using 1.8 mS CNTFET transconductance. The logic gate circuit has been developed by using new model of CNTFET. Delay, power, power delay product (PDP), leakage current and frequency response have been simulated and compared. |
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| Physical Description: | xviii, 221 leaves : ill. ; 30cm. |
| Bibliography: | Includes bibliographical references (leaves 153-167). |