Comparative study of silicon nanowire fet-simulation and experimental /
The demands and expectations of high performance devices using transistors particularly Field Effect Transistors (FET), have increased day by day. In order to obtain such decreased size with increased speed and performance, device scaling was implemented. However, making FET in smaller size is not a...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Gombak, Selangor :
Kulliyyah of Engineering,International Islamic University Malaysia,
2016
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| Subjects: | |
| Online Access: | http://studentrepo.iium.edu.my/handle/123456789/4413 |
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| LEADER | 029650000a22002770004500 | ||
|---|---|---|---|
| 008 | 171228t2016 my a g m 000 0 eng d | ||
| 040 | |a UIAM |b eng | ||
| 041 | |a eng | ||
| 043 | |a a-my--- | ||
| 050 | |a TK7871.95 | ||
| 100 | 1 | |a Yazeer, Mohamed Jameel | |
| 245 | 1 | |a Comparative study of silicon nanowire fet-simulation and experimental / |c by Mohamed Jameel Yazeer | |
| 260 | |a Gombak, Selangor : |b Kulliyyah of Engineering,International Islamic University Malaysia, |c 2016 | ||
| 300 | |a xvi, 80 leaves : |b ill. ; |c 30cm. | ||
| 502 | |a Thesis (MSEE)--International Islamic University Malaysia, 2016. | ||
| 504 | |a Includes bibliographical references (leaves 58-62). | ||
| 520 | |a The demands and expectations of high performance devices using transistors particularly Field Effect Transistors (FET), have increased day by day. In order to obtain such decreased size with increased speed and performance, device scaling was implemented. However, making FET in smaller size is not an easy task. One of the challenges with scaling the size of transistor is the Short Channel Effects (SCE) particularly the Drain Induced Barrier Lowering (DIBL), the ION/IOFF ration and the Subthreshold slope. The latest improved gate all around structure attracts a fair amount of interest nowadays because it exhibits a promising potential in suppressing the SCE parameters. In this work, a gate all around triangular cross section Silicon Nanowire FET (SiNW) with channel length of 300 nm was designed using COMSOL Multiphysics and its effectiveness in reducing the SCE parameters was investigated. Additionally, the obtained SCE parameters of the triangular SiNW FET were also compared with a same sized cylindrical cross section silicon nanowire FET and also with SCE parameters of commercial MOSFET. The 300 nm triangular and cylindrical SiNW FET designs and data simulations were carried out using COMSOL Multiphysics while the commercial MOSFET SCE parameters were extracted by using Keithley 4200 SCS apparatus. By analysing the obtained SCE parameters of the two designed SiNW FETs and the commercial MOSFET, the result shows that the triangular SiNW FET structure has shown greater potential in limiting the SCE when compared with the cylindrical SiNW FET as well as the commercial MOSFET. | ||
| 596 | |a 1 | ||
| 655 | 7 | |a Theses, IIUM local | |
| 690 | |a Dissertations, Academic |x Department of Electrical and Computer Engineering |z IIUM | ||
| 710 | 2 | |a International Islamic University Malaysia. |b Department of Electrical and Computer Engineering | |
| 856 | 4 | |u http://studentrepo.iium.edu.my/handle/123456789/4413 | |
| 900 | |a sbh-lfr | ||
| 999 | |c 437832 |d 469025 | ||
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| 952 | |0 0 |6 TS CDF TK 7871.95 Y35C 2016 |7 0 |8 THESES |9 855151 |a IIUM |b IIUM |c MULTIMEDIA |g 0.00 |o ts cdf TK 7871.95 Y35C 2016 |p 11100352264 |r 2018-03-08 |t 1 |v 0.00 |y THESISDIG | ||