Design and modeling of a clock data recovery (CDR) circuit /
Clock data recovery (CDR) circuits are in high demand due to development in communication technology such as improvements in transmit/receive processing and GHz transfer bandwidths via wired and wireless media. Large bandwidth data with high transfer rates encounter several major problems at the rec...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
Kuala Lumpur:
Kulliyyah of Engineering, International Islamic University Malaysia,
2013
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| 主題: | |
| 在線閱讀: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
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