Modelling of the reliability baseline for process control monitoring of kerf structures /

Miniaturization of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) beyond 0.1 μm has caused problems like short channel effect and leakage current which has lead to reliability issues. Therefore, reliability monitoring for miniaturized MOSFET is crucial in today's semiconductor indu...

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Bibliographic Details
Main Author: Ismah Binti Izuddin
Format: Thesis
Language:English
Published: Kuala Lumpur: Kulliyyah of Engineering, International Islamic University Malaysia, 2012
Subjects:
Online Access:http://studentrepo.iium.edu.my/handle/123456789/5000
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040 |a UIAM  |b eng 
041 |a eng 
043 |a a-my--- 
050 0 0 |a TA169 
100 0 |a Ismah Binti Izuddin 
245 1 |a Modelling of the reliability baseline for process control monitoring of kerf structures /  |c by Ismah Binti Izuddin 
260 |a Kuala Lumpur:   |b Kulliyyah of Engineering, International Islamic University Malaysia,   |c 2012 
300 |a xxii, 107[11] :  |b ill. ;  |c 30cm. 
500 |a Abstract in English and Arabic. 
500 |a "A thesis submitted in fulfilment of the requirements for the degree of Master of Science (Computer and information Engineering)."--On t.p. 
502 |a Thesis (MSc.CIE)--International Islamic University Malaysia, 2012. 
504 |a Includes bibliographical references (leaves 101-107). 
520 |a Miniaturization of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) beyond 0.1 μm has caused problems like short channel effect and leakage current which has lead to reliability issues. Therefore, reliability monitoring for miniaturized MOSFET is crucial in today's semiconductor industry. Currently in Infineon Technologies Kulim, unreliable MOSFET wafers are disposed based on productive dies reliability baseline alone. In order to get more reliable lot disposition decision, Product Chip Monitor-Wafer Level Reliability (PCM-WLR) is proposed to be performed. This project aims to develop a PCM-WLR model and to characterize 45 nm thick gate-oxide, trench DMOS technology. The motivation of this work is to establish the baseline of the dielectric and device reliability for the PCM-Kerf structure that will enhance the capability to perform lot disposition in the event of deviant measurement results. Different WLR test structures were stressed and a correlation study was performed with existing models. The tests done were Electrical Field Ramp (ERAMP), Step Stress Charge (SSQ), positive High Temperature Gate Stress (PHTGS) and three-terminal Charge Pumping (3T-CP). Total measurement accuracy for ERAMP is 88.52% under 175 °C and 125 °C temperature stress. Total measurement accuracy for SSQ is 90/90 (100% accurate) under 175 °C, 150 °C and 25 °C temperature stress. ERAMP and SSQ tests plots have shown uniform breakdown voltage. PHTGS tests are unstable for PCM-Kerf since some of the drift trends were not uniformly plotted. Only 38/53 (71.7%) of the test results under 175 °C and 150 °C were usable to create the baseline. The 3T-CP results met the expectations for all types of tests under 25 °C. Overall, the WLR tests results obtained are satisfactory and can be used as the baseline and that the experimental setups are applicable to other process technology except for the test parameter should be fine tuned to meet the functional specifications of the technology under test. 
596 |a 1 
650 0 |a Reliability (Engineering) 
650 0 |a Computer software  |x Reliability 
650 0 |a Reliability (Engineering)  |x Mathematical models 
655 7 |a Theses, IIUM local 
690 |a Dissertations, Academic  |x Department of Electrical and Computer Engineering  |z IIUM 
710 2 |a International Islamic University Malaysia.  |b Department of Electrical and Computer Engineering 
856 4 |u http://studentrepo.iium.edu.my/handle/123456789/5000 
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