High-Performance CMOS Clock And Data Recovery Circuit
In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of it...
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my-mmu-ep.10942010-08-05T03:38:43Z High-Performance CMOS Clock And Data Recovery Circuit 2006-09 Tan, Kok Siang QA76.75-76.765 Computer software In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption. 2006-09 Thesis http://shdl.mmu.edu.my/1094/ http://myto.perpun.net.my/metoalogin/logina.php masters Multimedia University Research Library |
| institution |
Multimedia University |
| collection |
MMU Institutional Repository |
| topic |
QA76.75-76.765 Computer software |
| spellingShingle |
QA76.75-76.765 Computer software Tan, Kok Siang High-Performance CMOS Clock And Data Recovery Circuit |
| description |
In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Tan, Kok Siang |
| author_facet |
Tan, Kok Siang |
| author_sort |
Tan, Kok Siang |
| title |
High-Performance CMOS Clock And Data Recovery Circuit |
| title_short |
High-Performance CMOS Clock And Data Recovery Circuit |
| title_full |
High-Performance CMOS Clock And Data Recovery Circuit |
| title_fullStr |
High-Performance CMOS Clock And Data Recovery Circuit |
| title_full_unstemmed |
High-Performance CMOS Clock And Data Recovery Circuit |
| title_sort |
high-performance cmos clock and data recovery circuit |
| granting_institution |
Multimedia University |
| granting_department |
Research Library |
| publishDate |
2006 |
| _version_ |
1747829289301049344 |