Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temp...
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2022
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| Summary: | The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temperature. The Tunnel Field Effect Transistor (TFET) is a promising future device owing to its sharp subthreshold swing (SS), which makes it an ideal device at low power supply. Steep switching TFETs can extend the scaling of the supply voltage while increasing energy efficiency for both digital and analog applications. However, these devices suffer from significant ambipolar current, which cannot be reduced by Dual Metal Gate (DMG) alone. The gate dielectric materials play a crucial role in reducing the ambipolar current. Analytical models can assist in designing, simulating, and providing a more in-depth understanding of the device's working electrical characteristics. This study presents comprehensive analytical models for the hetero-gate dielectric (HDG) TFET's channel potential distribution, tunneling width, and threshold voltage. The models were developed using the parabolic potential approximation method to solve the 2-D Poisson's equation. The accuracy of the proposed model was verified by comparing the results with existing literature and 2-D ATLAS TCAD simulator results, which showed close agreement. The research reveals that as the length of the high-k region near the source decreases, the conduction band becomes shallow, making band-toband tunneling more challenging and increasing the threshold voltage. As a result, the device offers better gm, lower SS, lower leakage, and more significant drive currents due to weaker insulating barriers at the tunneling junction. A higher effective dielectric constant provides better gate coupling and lower trap density. Additionally, the ON current of the device can be increased considerably by reducing the ambipolar current appreciably by choosing gate material of higher work function near the source region. In conclusion, the proposed HDG structure effectively suppresses the ambipolar current, enhances the drive current, and reduces short channel effect (SCE). |
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