Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor

The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temp...

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Main Author:	Tan, Chun Fui
Format:	Thesis
Published:	2022
Subjects:	TK7871 Electronics > Materials
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id	my-mmu-ep.11544
record_format	uketd_dc
spelling	my-mmu-ep.115442023-07-18T05:34:17Z Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor 2022-10 Tan, Chun Fui TK7871 Electronics--Materials The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temperature. The Tunnel Field Effect Transistor (TFET) is a promising future device owing to its sharp subthreshold swing (SS), which makes it an ideal device at low power supply. Steep switching TFETs can extend the scaling of the supply voltage while increasing energy efficiency for both digital and analog applications. However, these devices suffer from significant ambipolar current, which cannot be reduced by Dual Metal Gate (DMG) alone. The gate dielectric materials play a crucial role in reducing the ambipolar current. Analytical models can assist in designing, simulating, and providing a more in-depth understanding of the device's working electrical characteristics. This study presents comprehensive analytical models for the hetero-gate dielectric (HDG) TFET's channel potential distribution, tunneling width, and threshold voltage. The models were developed using the parabolic potential approximation method to solve the 2-D Poisson's equation. The accuracy of the proposed model was verified by comparing the results with existing literature and 2-D ATLAS TCAD simulator results, which showed close agreement. The research reveals that as the length of the high-k region near the source decreases, the conduction band becomes shallow, making band-toband tunneling more challenging and increasing the threshold voltage. As a result, the device offers better gm, lower SS, lower leakage, and more significant drive currents due to weaker insulating barriers at the tunneling junction. A higher effective dielectric constant provides better gate coupling and lower trap density. Additionally, the ON current of the device can be increased considerably by reducing the ambipolar current appreciably by choosing gate material of higher work function near the source region. In conclusion, the proposed HDG structure effectively suppresses the ambipolar current, enhances the drive current, and reduces short channel effect (SCE). 2022-10 Thesis http://shdl.mmu.edu.my/11544/ http://erep.mmu.edu.my/ phd doctoral Multimedia University Faculty of Engineering and Technology (FET) EREP ID: 10859
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK7871 Electronics--Materials
spellingShingle	TK7871 Electronics--Materials Tan, Chun Fui Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
description	The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temperature. The Tunnel Field Effect Transistor (TFET) is a promising future device owing to its sharp subthreshold swing (SS), which makes it an ideal device at low power supply. Steep switching TFETs can extend the scaling of the supply voltage while increasing energy efficiency for both digital and analog applications. However, these devices suffer from significant ambipolar current, which cannot be reduced by Dual Metal Gate (DMG) alone. The gate dielectric materials play a crucial role in reducing the ambipolar current. Analytical models can assist in designing, simulating, and providing a more in-depth understanding of the device's working electrical characteristics. This study presents comprehensive analytical models for the hetero-gate dielectric (HDG) TFET's channel potential distribution, tunneling width, and threshold voltage. The models were developed using the parabolic potential approximation method to solve the 2-D Poisson's equation. The accuracy of the proposed model was verified by comparing the results with existing literature and 2-D ATLAS TCAD simulator results, which showed close agreement. The research reveals that as the length of the high-k region near the source decreases, the conduction band becomes shallow, making band-toband tunneling more challenging and increasing the threshold voltage. As a result, the device offers better gm, lower SS, lower leakage, and more significant drive currents due to weaker insulating barriers at the tunneling junction. A higher effective dielectric constant provides better gate coupling and lower trap density. Additionally, the ON current of the device can be increased considerably by reducing the ambipolar current appreciably by choosing gate material of higher work function near the source region. In conclusion, the proposed HDG structure effectively suppresses the ambipolar current, enhances the drive current, and reduces short channel effect (SCE).
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Tan, Chun Fui
author_facet	Tan, Chun Fui
author_sort	Tan, Chun Fui
title	Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
title_short	Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
title_full	Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
title_fullStr	Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
title_full_unstemmed	Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
title_sort	mathematical modelling and characterisation of low power hetero-gate-dielectric tunnel field effect transistor
granting_institution	Multimedia University
granting_department	Faculty of Engineering and Technology (FET)
publishDate	2022
_version_	1776101417283485696

Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor

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