Mathematical modelling and characterisation of low power Hetero-Gate-Dielectric tunnel field effect transistor
The reduction of power consumption is a crucial aspect of the design of submicron logic circuits, which can be accomplished by scaling the supply voltage. Contemporary Field Effect Transistor (FET) circuits necessitate a minimum of 60 mV of gate voltage to achieve superior current drive at room temp...
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Main Author: | Tan, Chun Fui |
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Format: | Thesis |
Published: |
2022
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