Fast-Lock Low -Jitter Delay Locked Loop
In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.
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| 格式: | Thesis |
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2007
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| 總結: | In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed. |
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