Fast-Lock Low -Jitter Delay Locked Loop

In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.

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书目详细资料
主要作者:	Soh, Lip Kai
格式:	Thesis
出版:	2007
主题:	TK7800-8360 Electronics
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