Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder cir...

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Main Author:	C., Senthilpari
Format:	Thesis
Published:	2009
Subjects:	TK7800-8360 Electronics
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id	my-mmu-ep.1786
record_format	uketd_dc
spelling	my-mmu-ep.17862011-01-11T03:57:07Z Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach 2009-01 C., Senthilpari TK7800-8360 Electronics This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder circuit is designed completely by using the Shannon theorem. The Mixed-Shannon and full Shannon adder cells are used in the implementation of 8-bit array multipliers, namely, the Braun array, CSM and Baugh-Wooley multipliers. Output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulation results. 2009-01 Thesis http://shdl.mmu.edu.my/1786/ http://vlib.mmu.edu.my/diglib/login/dlusr/login.php phd doctoral Multimedia University Research Library
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics C., Senthilpari Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
description	This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder circuit is designed completely by using the Shannon theorem. The Mixed-Shannon and full Shannon adder cells are used in the implementation of 8-bit array multipliers, namely, the Braun array, CSM and Baugh-Wooley multipliers. Output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulation results.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	C., Senthilpari
author_facet	C., Senthilpari
author_sort	C., Senthilpari
title	Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
title_short	Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
title_full	Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
title_fullStr	Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
title_full_unstemmed	Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
title_sort	design of 32-bit arithmetic logic unit using shannon theorem based adder approach
granting_institution	Multimedia University
granting_department	Research Library
publishDate	2009
_version_	1747829453847789568

Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

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