Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder cir...
Saved in:
Main Author: | C., Senthilpari |
---|---|
Format: | Thesis |
Published: |
2009
|
Subjects: | |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
VLSI Design Of A Bit Serial Arithmetic Logic Unit
by: Lee, Tiong Kiat
Published: (2003) -
A low power and fast CMOS arithmetic logic unit
by: Zulkifli, Nur Umaira
Published: (2015) -
Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
by: Lim, Nguk Jie
Published: (2015) -
Performance Analysis Of Different Hash Functions Using Bloom Filter For Network Intrusion Detection Systems In 32-Bit And 64-Bit Computer Operation Mode.
by: Tan , Beng Ghee
Published: (2016) -
Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
by: Saadatzi, Mohammadsadegh
Published: (2015)