Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder cir...

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書目詳細資料
主要作者:	C., Senthilpari
格式:	Thesis
出版:	2009
主題:	TK7800-8360 Electronics
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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