Low Power Design And Layout Techniques For CMOS Mixed - Signal Circuits

Low Power Design And Layout Techniques For CMOS Mixed - Signal Circuits

This thesis investigates the proposed layout techniques that imitates the triple well process by doing it on the conventional process technology. This proposed layout is fabricated and the results show that the layout techniques managers to change the threshold voltage. However, there are certain is...

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書目詳細資料
主要作者:	Abdul Khalek, Mohd Faizal
格式:	Thesis
出版:	2009
主題:	TK Electrical engineering Electronics Nuclear engineering
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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