Design Of Power Efficient Pass Transistor Logic Based Full Adder Circut For Digital Finite Impluse Response Filter
Digital Finite Impulse Responses (FIR) filter plays a significant role in Digital Signal Processing (DSP). FIR digital filters block certain components of the input frequency. Subsequently, they convey the original signal with the eliminated components to the filter’s output. The advantages of the...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 出版: |
2019
|
| 主题: | |
| 标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
| 总结: | Digital Finite Impulse Responses (FIR) filter plays a significant role in Digital Signal Processing (DSP). FIR digital filters block certain components of the input frequency. Subsequently, they convey the original signal with the eliminated components to the filter’s output. The advantages of the FIR’s digital filters include linear phase shift, low coefficient sensitivity, and stability. Researchers have thoroughly researched the power dissipation, and efficiency-performance of the FIR digital filters, as they utilize the arithmetic operations, including addition, and multiplication in the DSP system. Adder is a crucially important arithmetic operation which is employed as part of the building block in the FIR filter. In this study, the employment of the power-efficient Pass Transistor Logic (PTL) alongside Negative Channel Metal Oxide Semiconductors (NMOS) was proposed and presented. NMOS transistors were employed for the implementation of digital logic circuits. The higher speed associated with NMOS was due to the electrons that were the main carriers in comparison to holes, which were slower carriers. Furthermore, the advantage associated with the use of PTL alongside NMOS transistors was the smaller area required, as well as a reduction in complexity due to the use of fewer transistors. However, the disadvantages of employment of PTL with NMOS transistors were the threshold voltage and V drop in multi-bit full adder circuits. In order to resolve this, a sense amplifier was introduced in order to enable output voltage restoration in the multi-bit full adder stages. |
|---|