A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
An iterative mincut heunstic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typicaUy needed. To deal with cells of various size , the algorithm progresses by moving o...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
1997
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| 在線閱讀: | https://ir.uitm.edu.my/id/eprint/101532/1/101532.pdf |
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