Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm...
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2013
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my-uitm-ir.1028892024-11-11T06:57:12Z Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi 2013 Mohd Zaidi, Mohd Khushairi Applications of electric power This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps. 2013 Thesis https://ir.uitm.edu.my/id/eprint/102889/ https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf text en public degree Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering Hassan, Lailatul |
| institution |
Universiti Teknologi MARA |
| collection |
UiTM Institutional Repository |
| language |
English |
| advisor |
Hassan, Lailatul |
| topic |
Applications of electric power |
| spellingShingle |
Applications of electric power Mohd Zaidi, Mohd Khushairi Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| description |
This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps. |
| format |
Thesis |
| qualification_level |
Bachelor degree |
| author |
Mohd Zaidi, Mohd Khushairi |
| author_facet |
Mohd Zaidi, Mohd Khushairi |
| author_sort |
Mohd Zaidi, Mohd Khushairi |
| title |
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| title_short |
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| title_full |
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| title_fullStr |
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| title_full_unstemmed |
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi |
| title_sort |
power efficient 64-bit dynamic comparator using 0.18um technology / mohd khushairi mohd zaidi |
| granting_institution |
Universiti Teknologi MARA (UiTM) |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2013 |
| url |
https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf |
| _version_ |
1818588060738125824 |