Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm...
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| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Online Access: | https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf |
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