GeTe multi-level phase change memory with separate heater layer/ Muhammad Syamimi Rozano

Phase change memory (PCM) is one of the promising technology for future in nonvolatile solid state memory. The concept of phase change memory is the changing state from amorphous to crystalline state. The temperature of changing the amorphous to crystalline is differed according to the phase change...

Full description

Saved in:
Bibliographic Details
Main Author: Rozano, Muhammad Syamimi
Format: Thesis
Language:English
Published: 2015
Subjects:
Online Access:https://ir.uitm.edu.my/id/eprint/102962/1/102962.pdf
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Phase change memory (PCM) is one of the promising technology for future in nonvolatile solid state memory. The concept of phase change memory is the changing state from amorphous to crystalline state. The temperature of changing the amorphous to crystalline is differed according to the phase change material. Ge2Se2T5 is the common phase change material for phase change memory. However the crystalline state for Ge2Se2T5 is (450K-900K). After 900K, the phase change material will melt and become amorphous state. There are few reasons of conducting this project. Firstly, this project is conducting in order to overcome the rapid changes in conventional phase change memory layer which is hardly to control the crystallization process. Then, the implementation of Germanium Telluride and Silicon Carbide (SiC) will be used for the design in order to achieve the multi-level memory. In this project, the phase change memory is designed by using Germanium Telluride as the phase change layer. The top and bottom electrodes for this structure are Titanium Nitride. Then, the heater for this structure is Silicon Carbide and silicon dioxide as the insulator for the structure. The substrate for this structure is Glass (quartz). Figure 1 shows the structure for the design multilevel phase change memory. COMSOL 4.4 will be used for the simulation software. A 100ns SET pulse with time dependent from 0.1 to 3V in order to achieve four bits of multilevel memory.