Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom
Strained technology is used to enhance the performance of the CMOS that involves physically stretching or compressing the silicon crystal lattice, which in turn increasing carrier mobility without having to make them smaller. Shallow-trench isolation (STI) and silicidation process is the way of stra...
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2010
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| Online Access: | https://ir.uitm.edu.my/id/eprint/102995/1/102995.pdf |
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my-uitm-ir.1029952024-09-30T06:40:06Z Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom 2010 Baharom, Abu Hudzaifah Strained technology is used to enhance the performance of the CMOS that involves physically stretching or compressing the silicon crystal lattice, which in turn increasing carrier mobility without having to make them smaller. Shallow-trench isolation (STI) and silicidation process is the way of strained technology process applied in this investigation. This project discussed on the effect of strain technology on 90nm CMOS device performance focusing on threshold voltage and drain current parameter. Athena and Atlas simulators were used to simulate the process and to characterize the electrical properties respectively. It can be concluded that CMOS with STI and Silicide have better performance than the conventional CMOS. It shows that drain current with STI have been improved by 10% in PMOS and 90.7% in NMOS. While by using Silicide it shows 5.4% in PMOS and 1.82% in NMOS improvement. 2010 Thesis https://ir.uitm.edu.my/id/eprint/102995/ https://ir.uitm.edu.my/id/eprint/102995/1/102995.pdf text en public degree Universiti Teknologi MARA Faculty of Electrical Engineering |
| institution |
Universiti Teknologi MARA |
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UiTM Institutional Repository |
| language |
English |
| description |
Strained technology is used to enhance the performance of the CMOS that involves physically stretching or compressing the silicon crystal lattice, which in turn increasing carrier mobility without having to make them smaller. Shallow-trench isolation (STI) and silicidation process is the way of strained technology process applied in this investigation. This project discussed on the effect of strain technology on 90nm CMOS device performance focusing on threshold voltage and drain current parameter. Athena and Atlas simulators were used to simulate the process and to characterize the electrical properties respectively. It can be concluded that CMOS with STI and Silicide have better performance than the conventional CMOS. It shows that drain current with STI have been improved by 10% in PMOS and 90.7% in NMOS. While by using Silicide it shows 5.4% in PMOS and 1.82% in NMOS improvement. |
| format |
Thesis |
| qualification_level |
Bachelor degree |
| author |
Baharom, Abu Hudzaifah |
| spellingShingle |
Baharom, Abu Hudzaifah Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| author_facet |
Baharom, Abu Hudzaifah |
| author_sort |
Baharom, Abu Hudzaifah |
| title |
Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| title_short |
Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| title_full |
Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| title_fullStr |
Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| title_full_unstemmed |
Investigation of shallow trench isolation and silicide effect on 90nm CMOS devices / Abu Hudzaifah Baharom |
| title_sort |
investigation of shallow trench isolation and silicide effect on 90nm cmos devices / abu hudzaifah baharom |
| granting_institution |
Universiti Teknologi MARA |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2010 |
| url |
https://ir.uitm.edu.my/id/eprint/102995/1/102995.pdf |
| _version_ |
1811769241911689216 |