An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf

Scheduling mechanism is the process of dynamically allocating radio resources (time and frequency) to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution (LTE) base station, Evolved Node B. Since the...

Full description

Saved in:

Bibliographic Details
Main Author:	Yusuf, Yusmardiah
Format:	Thesis
Language:	English
Published:	2017
Subjects:	Computer networks General works Traffic monitoring
Online Access:	https://ir.uitm.edu.my/id/eprint/37180/1/37180.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-uitm-ir.37180
record_format	uketd_dc
spelling	my-uitm-ir.371802023-08-21T02:03:29Z An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf 2017 Yusuf, Yusmardiah Computer networks. General works. Traffic monitoring Scheduling mechanism is the process of dynamically allocating radio resources (time and frequency) to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution (LTE) base station, Evolved Node B. Since the implementation of scheduling algorithm is an open issue in LTE, many packet scheduling algorithms have been proposed by researchers. For instance, various scheduling algorithms which offer several techniques in handling resources to the users have been developed such as Modified Largest Weighted Delay First (MLWDF), Proportional Fairness (PF) and Maximum Rate. This thesis investigates the implementation of the Exponential and Blind Equal Throughput (EXP-BET) scheduling algorithm on the FPGA platform. MATLAB Simulink and System Generator are the tools used for the prototyping. The design using Simulink and System generator can greatly reduce the process cycle from the algorithm to hardware. The metric equation of the EXP-BET algorithm is modelled and simulated using the MATLAB Simulink environment and System Generator tool provided by Xilinx. This design has utilized only 10% of available resources on Virtex-6 device. Then, it is tested on the FPGA using the properties of hardware co-simulation method. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm and compared against the manual calculation. 2017 Thesis https://ir.uitm.edu.my/id/eprint/37180/ https://ir.uitm.edu.my/id/eprint/37180/1/37180.pdf text en public masters Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering Mohd Ali, Darmawaty
institution	Universiti Teknologi MARA
collection	UiTM Institutional Repository
language	English
advisor	Mohd Ali, Darmawaty
topic	Computer networks General works Traffic monitoring
spellingShingle	Computer networks General works Traffic monitoring Yusuf, Yusmardiah An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
description	Scheduling mechanism is the process of dynamically allocating radio resources (time and frequency) to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution (LTE) base station, Evolved Node B. Since the implementation of scheduling algorithm is an open issue in LTE, many packet scheduling algorithms have been proposed by researchers. For instance, various scheduling algorithms which offer several techniques in handling resources to the users have been developed such as Modified Largest Weighted Delay First (MLWDF), Proportional Fairness (PF) and Maximum Rate. This thesis investigates the implementation of the Exponential and Blind Equal Throughput (EXP-BET) scheduling algorithm on the FPGA platform. MATLAB Simulink and System Generator are the tools used for the prototyping. The design using Simulink and System generator can greatly reduce the process cycle from the algorithm to hardware. The metric equation of the EXP-BET algorithm is modelled and simulated using the MATLAB Simulink environment and System Generator tool provided by Xilinx. This design has utilized only 10% of available resources on Virtex-6 device. Then, it is tested on the FPGA using the properties of hardware co-simulation method. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm and compared against the manual calculation.
format	Thesis
qualification_level	Master's degree
author	Yusuf, Yusmardiah
author_facet	Yusuf, Yusmardiah
author_sort	Yusuf, Yusmardiah
title	An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
title_short	An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
title_full	An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
title_fullStr	An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
title_full_unstemmed	An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf
title_sort	fpga implementation of exp-bet scheduling algorithm in lte networks / yusmardiah yusuf
granting_institution	Universiti Teknologi MARA (UiTM)
granting_department	Faculty of Electrical Engineering
publishDate	2017
url	https://ir.uitm.edu.my/id/eprint/37180/1/37180.pdf
_version_	1783734395364966400

An FPGA implementation of exp-bet scheduling algorithm in LTE networks / Yusmardiah Yusuf

Similar Items