Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan

This project implement a algorithm for the optimal transistor chaining problem in CMOS functional cell layout based on Uehara and vanCleemput's layout style [1] which assumed that the height of each logic module layout is constant and performed the optimisation by decomposing the graph module i...

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Main Author:	Misnan, Azizi
Format:	Thesis
Language:	English
Published:	1997
Online Access:	https://ir.uitm.edu.my/id/eprint/74388/1/74388.pdf
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id	my-uitm-ir.74388
record_format	uketd_dc
spelling	my-uitm-ir.743882023-06-08T08:08:47Z Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan 1997 Misnan, Azizi This project implement a algorithm for the optimal transistor chaining problem in CMOS functional cell layout based on Uehara and vanCleemput's layout style [1] which assumed that the height of each logic module layout is constant and performed the optimisation by decomposing the graph module into a minimum number of sub graph having a dual Euler (d-Euler) trail.. The algorithm takes a transistor level circuit schematic and the outputs a minimum set of chains. Searching for possible abutment between the transistor pairs are modelled as a bipartite graph. A depth - first search algorithm is used to search for optimal chaining. Theorems on number of branches needed to be explored at each node of search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables us to prune the search tree efficiently. The algorithm will be implemented and tested in this project using C language. The result will be compared with euler's path algorithm using heuristic search and a pseudo input to find the minimum interlace. 1997 Thesis https://ir.uitm.edu.my/id/eprint/74388/ https://ir.uitm.edu.my/id/eprint/74388/1/74388.pdf text en public degree Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering
institution	Universiti Teknologi MARA
collection	UiTM Institutional Repository
language	English
description	This project implement a algorithm for the optimal transistor chaining problem in CMOS functional cell layout based on Uehara and vanCleemput's layout style [1] which assumed that the height of each logic module layout is constant and performed the optimisation by decomposing the graph module into a minimum number of sub graph having a dual Euler (d-Euler) trail.. The algorithm takes a transistor level circuit schematic and the outputs a minimum set of chains. Searching for possible abutment between the transistor pairs are modelled as a bipartite graph. A depth - first search algorithm is used to search for optimal chaining. Theorems on number of branches needed to be explored at each node of search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables us to prune the search tree efficiently. The algorithm will be implemented and tested in this project using C language. The result will be compared with euler's path algorithm using heuristic search and a pseudo input to find the minimum interlace.
format	Thesis
qualification_level	Bachelor degree
author	Misnan, Azizi
spellingShingle	Misnan, Azizi Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
author_facet	Misnan, Azizi
author_sort	Misnan, Azizi
title	Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
title_short	Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
title_full	Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
title_fullStr	Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
title_full_unstemmed	Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
title_sort	synthesis of transistor-chaining algorithm for cmos cell layout using bipartite graph / azizi misnan
granting_institution	Universiti Teknologi MARA (UiTM)
granting_department	Faculty of Electrical Engineering
publishDate	1997
url	https://ir.uitm.edu.my/id/eprint/74388/1/74388.pdf
_version_	1783736021024768000

Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan

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