Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie

The model and design of the intellectual property (IP) core of serial peripheral interface (SPI) with Advanced Microcontroller Bus Architecture (AMBA) - Advanced Peripheral Bus (APB) interfacing are presented. The objectives of the project are to model and design a SPI that is interfacing with IP co...

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Main Author:	Sabparie, Muhammad Hafeez
Format:	Thesis
Language:	English
Published:	2022
Online Access:	https://ir.uitm.edu.my/id/eprint/75401/1/75401.pdf
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id	my-uitm-ir.75401
record_format	uketd_dc
spelling	my-uitm-ir.754012023-03-28T07:32:36Z Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie 2022 Sabparie, Muhammad Hafeez The model and design of the intellectual property (IP) core of serial peripheral interface (SPI) with Advanced Microcontroller Bus Architecture (AMBA) - Advanced Peripheral Bus (APB) interfacing are presented. The objectives of the project are to model and design a SPI that is interfacing with IP core of APB for sending and receiving data from a single slave to model APB-SPI controller with controllable data and designed with maximum operating frequency of 16 MHz and flexibility in all four clocking modes and finally to synthesize and validate the model of the SPI design. For this work, research regarding interfacing SPI with another core and designing the SPI itself is essential for the project. The design and simulation of SPI master and slave is based on Verilog coding. The Verilog code is the main language that is use for designing and running simulations for this project. SPI is one of the commonly used serial protocols that can send or receive data from a single or multi-slave. Due to proliferation of communication protocols and requirement of flexibility in communication, this work shows how an architecture of APB-SPI controller with controllable data width and an operating frequency of 16MHz is designed. The SPI is simulated, verified, synthesized, carry a layout design and routed using tools such from the electronic design automation (EDA) tools which is Synopsys, simulation software which are ModelSim and Quartus prime lite. The design and implementation of SPI model interface is targeted to be used in Low Power Wireless Microcontroller Unit and its specification is based on Nordic Wireless RF System on Chip. The modes of SPI also play important role in this work where this protocol can run through four modes that corresponds to four possible clocking configurations. The results showed that the core of SPI was successfully modelled and designed with maximum operating frequency of 16 MHz and flexibility in all four clocking modes. The ASIC design of this work consumed an area of 27750 um2 and a power of 47.12uW by using Silterra 0.18um for future fabrication CMOS process. 2022 Thesis https://ir.uitm.edu.my/id/eprint/75401/ https://ir.uitm.edu.my/id/eprint/75401/1/75401.pdf text en public masters Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering Saparon, Azilah
institution	Universiti Teknologi MARA
collection	UiTM Institutional Repository
language	English
advisor	Saparon, Azilah
description	The model and design of the intellectual property (IP) core of serial peripheral interface (SPI) with Advanced Microcontroller Bus Architecture (AMBA) - Advanced Peripheral Bus (APB) interfacing are presented. The objectives of the project are to model and design a SPI that is interfacing with IP core of APB for sending and receiving data from a single slave to model APB-SPI controller with controllable data and designed with maximum operating frequency of 16 MHz and flexibility in all four clocking modes and finally to synthesize and validate the model of the SPI design. For this work, research regarding interfacing SPI with another core and designing the SPI itself is essential for the project. The design and simulation of SPI master and slave is based on Verilog coding. The Verilog code is the main language that is use for designing and running simulations for this project. SPI is one of the commonly used serial protocols that can send or receive data from a single or multi-slave. Due to proliferation of communication protocols and requirement of flexibility in communication, this work shows how an architecture of APB-SPI controller with controllable data width and an operating frequency of 16MHz is designed. The SPI is simulated, verified, synthesized, carry a layout design and routed using tools such from the electronic design automation (EDA) tools which is Synopsys, simulation software which are ModelSim and Quartus prime lite. The design and implementation of SPI model interface is targeted to be used in Low Power Wireless Microcontroller Unit and its specification is based on Nordic Wireless RF System on Chip. The modes of SPI also play important role in this work where this protocol can run through four modes that corresponds to four possible clocking configurations. The results showed that the core of SPI was successfully modelled and designed with maximum operating frequency of 16 MHz and flexibility in all four clocking modes. The ASIC design of this work consumed an area of 27750 um2 and a power of 47.12uW by using Silterra 0.18um for future fabrication CMOS process.
format	Thesis
qualification_level	Master's degree
author	Sabparie, Muhammad Hafeez
spellingShingle	Sabparie, Muhammad Hafeez Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
author_facet	Sabparie, Muhammad Hafeez
author_sort	Sabparie, Muhammad Hafeez
title	Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
title_short	Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
title_full	Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
title_fullStr	Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
title_full_unstemmed	Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie
title_sort	design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / muhammad hafeez sabparie
granting_institution	Universiti Teknologi MARA (UiTM)
granting_department	Faculty of Electrical Engineering
publishDate	2022
url	https://ir.uitm.edu.my/id/eprint/75401/1/75401.pdf
_version_	1783736052400259072

Design of serial peripheral interface with flexible modes and frequency for advanced microcontroller bus architecture-advanced peripheral bus interface / Muhammad Hafeez Sabparie

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