Analog ic design of the digital to analog converter in 0.5um CMOS technology / Norsyidah Abdullah
This thesis presents the design of a DAC in a HP 0.5urn SCN3M Complementary Metal Oxide Semiconductor (CMOS) technology process. Full custom design flow is implemented in which the design starts with schematic entry foliowed by simulation for characterization purpose and validation. The design is ba...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2006
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/98422/1/98422.PDF |
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| Summary: | This thesis presents the design of a DAC in a HP 0.5urn SCN3M Complementary Metal Oxide Semiconductor (CMOS) technology process. Full custom design flow is implemented in which the design starts with schematic entry foliowed by simulation for characterization purpose and validation. The design is based on basic digital to analog architecture which consists of resistor and transistor. This architecture provides both good DNL and INL characteristics by the R2R DAC circuit. Furthermore, the MOSFETs' W/L factor of the digital to analog circuit also contributes to the characteristics improvement. The results that were obtained through simulations showed that the proposed R2R DAC achieved power consumption of 1.42mW and for Voltage biased DAC with current mirror input achieved power consumption of 202.925uW with supply voltage of5V. The goal of this project was to outline the design process and testing for a simple digital-to-analog converter. The R-2R design has been shown to be effective with respect to linearity and total harmonie distortion |
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