8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this arc...
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| 格式: | Thesis |
| 语言: | English |
| 出版: |
2006
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| 主题: | |
| 在线阅读: | https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf |
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| 总结: | This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this architecture, the performance specification in terms of power consumption, resolution and speed are measured. The architecture is implemented by using the full custom design approaches. The design starts with the schematic entry followed by simulation for characterization purpose and validation. The power consumption of 3.59mW with resolution of 8-bit was achieved through simulations of the design. The speed was 125kHz with the supply voltage of 5V. The delay was measured in terms of clock cycle time because the layout of the architecture was not designed in this thesis. The conversion time and conversion rate was 8us and lMS/s respectively. |
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