8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim

This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this arc...

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Main Author:	Abdul Halim, Zuhaila
Format:	Thesis
Language:	English
Published:	2006
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf
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id	my-uitm-ir.98646
record_format	uketd_dc
spelling	my-uitm-ir.986462024-08-22T09:38:14Z 8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim 2006 Abdul Halim, Zuhaila TK Electrical engineering. Electronics. Nuclear engineering This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this architecture, the performance specification in terms of power consumption, resolution and speed are measured. The architecture is implemented by using the full custom design approaches. The design starts with the schematic entry followed by simulation for characterization purpose and validation. The power consumption of 3.59mW with resolution of 8-bit was achieved through simulations of the design. The speed was 125kHz with the supply voltage of 5V. The delay was measured in terms of clock cycle time because the layout of the architecture was not designed in this thesis. The conversion time and conversion rate was 8us and lMS/s respectively. 2006 Thesis https://ir.uitm.edu.my/id/eprint/98646/ https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf text en public degree Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering Abdullah, Fazlida Hanim
institution	Universiti Teknologi MARA
collection	UiTM Institutional Repository
language	English
advisor	Abdullah, Fazlida Hanim
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Abdul Halim, Zuhaila 8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
description	This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this architecture, the performance specification in terms of power consumption, resolution and speed are measured. The architecture is implemented by using the full custom design approaches. The design starts with the schematic entry followed by simulation for characterization purpose and validation. The power consumption of 3.59mW with resolution of 8-bit was achieved through simulations of the design. The speed was 125kHz with the supply voltage of 5V. The delay was measured in terms of clock cycle time because the layout of the architecture was not designed in this thesis. The conversion time and conversion rate was 8us and lMS/s respectively.
format	Thesis
qualification_level	Bachelor degree
author	Abdul Halim, Zuhaila
author_facet	Abdul Halim, Zuhaila
author_sort	Abdul Halim, Zuhaila
title	8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
title_short	8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
title_full	8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
title_fullStr	8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
title_full_unstemmed	8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
title_sort	8-bit successive approximation register analog-to-digital (sar adc) logic design / zuhaila abdul halim
granting_institution	Universiti Teknologi MARA (UiTM)
granting_department	Faculty of Electrical Engineering
publishDate	2006
url	https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf
_version_	1811768950401269760

8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim

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