8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim

8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim

This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this arc...

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書目詳細資料
主要作者:	Abdul Halim, Zuhaila
格式:	Thesis
語言:	English
出版:	2006
主題:	TK Electrical engineering Electronics Nuclear engineering
在線閱讀:	https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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