An efficient modified booth multiplier architecture

Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth...

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Main Author:	Razaidi, Hussin
Format:	Thesis
Language:	English
Subjects:	Multiplier Modified Booth Multiplier (MBM) Modified Booth Encoding (MBE) Computer architecture
Online Access:	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/1/full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/2/p.1-24.pdf
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id	my-unimap-20815
record_format	uketd_dc
spelling	my-unimap-208152012-09-04T03:33:38Z An efficient modified booth multiplier architecture Razaidi, Hussin Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth Multiplier focused on high speed with a moderate increase in area. This was achieved by reducing the critical path delay in the basic element of the multiplier circuit. Multiplication is performed by generating the partial product of Modified Booth Encoding (MBE) and accumulating the entire partial product by an adder or compressor. The research began by examining the available encoding schemes used to generate the partial product and 4:2 compressor that are used to accumulate the partial product. The fastest MBE and the most efficient 4:2 compressor has been used to develop the multiplier. The multiplier performance was improved by adapting various methods such as Simplified Sign Extension (SSE) and a proper tree topology. The SSE method eliminated some counter or adders in a partial product row while the tree topology arrangement of the compressors and their interconnection accumulate the partial product. A Gajski’s rule had been used to evaluate the performance of the multiplier and the result shows that the new multiplier has reduced delays in producing the output. The new multiplier architecture has reduced delays to almost 2% to 7% compared to other multipliers. The high speed multiplier was then extended to develop a Floating Point (FP) multiplier. The FP multiplier had been successfully designed using Altera Quartus II software and implemented on MAX EPM7182SLC84-7 device. The result showed that the FP multiplier is 38% faster compared to conventional FP multiplier. In term of size, the FP multiplier is 26% bigger than conventional circuit. However the increase in area of the circuit can be tolerated since the aim was to enhance the speed of the FP Multiplier Universiti Malaysia Perlis (UniMAP) 2008 Thesis en http://dspace.unimap.edu.my/123456789/20815 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/1/full%20text.pdf 44e74b743ffefa3057d341017087628e http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/2/p.1-24.pdf 3e7bdf4c091549d91af4bd249405e353 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/3/license.txt 5917c1fbd14d1aaddc1ba2e530221548 Multiplier Modified Booth Multiplier (MBM) Modified Booth Encoding (MBE) Computer architecture School of Microelectronic Engineering
institution	Universiti Malaysia Perlis
collection	UniMAP Institutional Repository
language	English
topic	Multiplier Modified Booth Multiplier (MBM) Modified Booth Encoding (MBE) Computer architecture
spellingShingle	Multiplier Modified Booth Multiplier (MBM) Modified Booth Encoding (MBE) Computer architecture Razaidi, Hussin An efficient modified booth multiplier architecture
description	Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth Multiplier focused on high speed with a moderate increase in area. This was achieved by reducing the critical path delay in the basic element of the multiplier circuit. Multiplication is performed by generating the partial product of Modified Booth Encoding (MBE) and accumulating the entire partial product by an adder or compressor. The research began by examining the available encoding schemes used to generate the partial product and 4:2 compressor that are used to accumulate the partial product. The fastest MBE and the most efficient 4:2 compressor has been used to develop the multiplier. The multiplier performance was improved by adapting various methods such as Simplified Sign Extension (SSE) and a proper tree topology. The SSE method eliminated some counter or adders in a partial product row while the tree topology arrangement of the compressors and their interconnection accumulate the partial product. A Gajski’s rule had been used to evaluate the performance of the multiplier and the result shows that the new multiplier has reduced delays in producing the output. The new multiplier architecture has reduced delays to almost 2% to 7% compared to other multipliers. The high speed multiplier was then extended to develop a Floating Point (FP) multiplier. The FP multiplier had been successfully designed using Altera Quartus II software and implemented on MAX EPM7182SLC84-7 device. The result showed that the FP multiplier is 38% faster compared to conventional FP multiplier. In term of size, the FP multiplier is 26% bigger than conventional circuit. However the increase in area of the circuit can be tolerated since the aim was to enhance the speed of the FP Multiplier
format	Thesis
author	Razaidi, Hussin
author_facet	Razaidi, Hussin
author_sort	Razaidi, Hussin
title	An efficient modified booth multiplier architecture
title_short	An efficient modified booth multiplier architecture
title_full	An efficient modified booth multiplier architecture
title_fullStr	An efficient modified booth multiplier architecture
title_full_unstemmed	An efficient modified booth multiplier architecture
title_sort	efficient modified booth multiplier architecture
granting_institution	Universiti Malaysia Perlis (UniMAP)
granting_department	School of Microelectronic Engineering
url	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/1/full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/2/p.1-24.pdf
_version_	1747836770823700480

An efficient modified booth multiplier architecture

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