Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput

In general, the security is concerned of all types of information and data systems. Many standards to security are ranging from military to commerce and private communications. One essential aspect for secure communications is the private key cryptography. Recently most security applications and st...

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Main Author:	Rana Khazaal, Khudhair
Format:	Thesis
Language:	English
Subjects:	Parallel computing Spatial parallelism Data security Crytography Data Encryption Standard (DES) Field programmable gate arrays
Online Access:	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/2/Full%20text.pdf
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id	my-unimap-61623
record_format	uketd_dc
spelling	my-unimap-616232019-09-03T09:27:05Z Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput Rana Khazaal, Khudhair Dr. Muataz S. Hameed In general, the security is concerned of all types of information and data systems. Many standards to security are ranging from military to commerce and private communications. One essential aspect for secure communications is the private key cryptography. Recently most security applications and standards are defined to independent algorithm, which is allowing a choice from a set of cryptographic algorithms for the same purpose. Since Data Encryption Standard (DES) is still the most widely used private-key encryption algorithm, DES has a significant role in security applications. Field Programmable Gate Arrays (FPGA) is reconfigurable hardware devices and interesting phenomenon in embedded development. In the present work, DES algorithm implementation optimization has been achieved through the DES unit components replication to four concurrent DES functional units. This operation has been performed by using a spatial parallelism approach. The input/output data has been stored in the separated RAMs which it is dual port memories that supports the read and write processes concurrently. This approach is speedup the processing of data. Furthermore, the frequency which is supported by the board has been duplicated from 50 up to 200 MHz by utilizing the Phase Locked Loop (PLL) to avoid any delay of DES functional unit implementation. All of this has led to enhance and speedup the implementation of DES algorithm and increase throughput as well. The design and implementation is performed on Altera Nios II Embedded Evaluation Kit (NEEK) board. Universiti Malaysia Perlis (UniMAP) 2015 Thesis en http://dspace.unimap.edu.my:80/xmlui/handle/123456789/61623 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/1/Page%201-24.pdf 7eca0c68864480c926c196b33bab958f http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/2/Full%20text.pdf 1c400f737dc65b3cba1d3a42ba639b69 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/3/license.txt 8a4605be74aa9ea9d79846c1fba20a33 Parallel computing Spatial parallelism Data security Crytography Data Encryption Standard (DES) Field programmable gate arrays School of Computer and Communication Engineering
institution	Universiti Malaysia Perlis
collection	UniMAP Institutional Repository
language	English
advisor	Dr. Muataz S. Hameed
topic	Parallel computing Spatial parallelism Data security Crytography Data Encryption Standard (DES) Field programmable gate arrays
spellingShingle	Parallel computing Spatial parallelism Data security Crytography Data Encryption Standard (DES) Field programmable gate arrays Rana Khazaal, Khudhair Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
description	In general, the security is concerned of all types of information and data systems. Many standards to security are ranging from military to commerce and private communications. One essential aspect for secure communications is the private key cryptography. Recently most security applications and standards are defined to independent algorithm, which is allowing a choice from a set of cryptographic algorithms for the same purpose. Since Data Encryption Standard (DES) is still the most widely used private-key encryption algorithm, DES has a significant role in security applications. Field Programmable Gate Arrays (FPGA) is reconfigurable hardware devices and interesting phenomenon in embedded development. In the present work, DES algorithm implementation optimization has been achieved through the DES unit components replication to four concurrent DES functional units. This operation has been performed by using a spatial parallelism approach. The input/output data has been stored in the separated RAMs which it is dual port memories that supports the read and write processes concurrently. This approach is speedup the processing of data. Furthermore, the frequency which is supported by the board has been duplicated from 50 up to 200 MHz by utilizing the Phase Locked Loop (PLL) to avoid any delay of DES functional unit implementation. All of this has led to enhance and speedup the implementation of DES algorithm and increase throughput as well. The design and implementation is performed on Altera Nios II Embedded Evaluation Kit (NEEK) board.
format	Thesis
author	Rana Khazaal, Khudhair
author_facet	Rana Khazaal, Khudhair
author_sort	Rana Khazaal, Khudhair
title	Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
title_short	Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
title_full	Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
title_fullStr	Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
title_full_unstemmed	Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput
title_sort	enhance implementation of embedded concurrent des functional units using spatial parallelism approach on fpga for better throughput
granting_institution	Universiti Malaysia Perlis (UniMAP)
granting_department	School of Computer and Communication Engineering
url	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/61623/2/Full%20text.pdf
_version_	1747836847309979648

Enhance implementation of embedded concurrent DES functional units using Spatial Parallelism approach on FPGA for better throughput

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