Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
Single-electron transistor (SET) is one of the promising nanotechnologies and distinguished by a very small device size and low power dissipation. This project explains the SET mask design, SET process flow development, and SET process and device simulation. The SET mask design consists of four l...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | أطروحة |
| اللغة: | English |
| الموضوعات: | |
| الوصول للمادة أونلاين: | http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/2/Full%20text.pdf |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| id |
my-unimap-63459 |
|---|---|
| record_format |
uketd_dc |
| spelling |
my-unimap-634592019-11-29T07:34:53Z Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication Amiza, Rasmi Uda Hashim, Assoc. Prof. Dr. Single-electron transistor (SET) is one of the promising nanotechnologies and distinguished by a very small device size and low power dissipation. This project explains the SET mask design, SET process flow development, and SET process and device simulation. The SET mask design consists of four level masks namely source and drain mask, polysilicon gate mask, contact mask, and metal mask. These masks were designed in nanometer (10-9 m) size using ELPHY Quantum GDS II Editor Software. The source and drain mask is connected by a nanowire placed between source and drain regions. The nanowire is designed with dimension of approximately 100 nm long and 10 nm wide. The process flow which includes the detailed parameters is developed for SET process and device simulation. This process flow consists of ten process modules include wafer cleaning process, material deposition, source/drain and nanowire formation , thermal oxidation, polysilicon deposition, polysilicon gate formation, source/drain implantation, contact formation, metal deposition and formation, and finally annealing and alloying process. The Synopsys TCAD simulation tools are utilized in SET process and device simulation work. The process and device simulation result shows that the single-electron transistor design with a 100 nm length and 10 nm width of the nanowire is working at room temperature (300 K) operation with a capacitance 0.4297 x 10-18F and a charging energy 186.4 meV. Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM) 2006-04 Thesis en http://dspace.unimap.edu.my:80/xmlui/handle/123456789/63459 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/1/Page%201-24.pdf 7b62059351cca546224561efe8983f02 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/2/Full%20text.pdf 91b7e6e83a55528811dd5c5dbdb8e600 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/3/license.txt 8a4605be74aa9ea9d79846c1fba20a33 Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices School of Microelectronic Engineering |
| institution |
Universiti Malaysia Perlis |
| collection |
UniMAP Institutional Repository |
| language |
English |
| advisor |
Uda Hashim, Assoc. Prof. Dr. |
| topic |
Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices |
| spellingShingle |
Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices Amiza, Rasmi Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| description |
Single-electron transistor (SET) is one of the promising nanotechnologies and
distinguished by a very small device size and low power dissipation. This project explains
the SET mask design, SET process flow development, and SET process and device
simulation. The SET mask design consists of four level masks namely source and drain
mask, polysilicon gate mask, contact mask, and metal mask. These masks were designed in
nanometer (10-9 m) size using ELPHY Quantum GDS II Editor Software. The source and
drain mask is connected by a nanowire placed between source and drain regions. The
nanowire is designed with dimension of approximately 100 nm long and 10 nm wide. The
process flow which includes the detailed parameters is developed for SET process and
device simulation. This process flow consists of ten process modules include wafer
cleaning process, material deposition, source/drain and nanowire formation , thermal
oxidation, polysilicon deposition, polysilicon gate formation, source/drain implantation,
contact formation, metal deposition and formation, and finally annealing and alloying
process. The Synopsys TCAD simulation tools are utilized in SET process and device
simulation work. The process and device simulation result shows that the single-electron
transistor design with a 100 nm length and 10 nm width of the nanowire is working at room
temperature (300 K) operation with a capacitance 0.4297 x 10-18F and a charging energy
186.4 meV. |
| format |
Thesis |
| author |
Amiza, Rasmi |
| author_facet |
Amiza, Rasmi |
| author_sort |
Amiza, Rasmi |
| title |
Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| title_short |
Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| title_full |
Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| title_fullStr |
Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| title_full_unstemmed |
Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication |
| title_sort |
design, simulation and process development for sol single-electron transistor (set) fabrication |
| granting_institution |
Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM) |
| granting_department |
School of Microelectronic Engineering |
| url |
http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/63459/2/Full%20text.pdf |
| _version_ |
1747836857209585664 |