Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity

The condition that drives a system to complete the processing of a number of functions within a given amount of time is called the real-time system. A projective missile system’s processing platforms face two major issues: high cost and structureal complexity. The system structure’s complexity is a...

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Format:	Thesis
Language:	English
Subjects:	Embedded computer systems Field programmable gate arrays Embedded system
Online Access:	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/4/Hussein%20Ibrahim.pdf
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spelling	my-unimap-724402021-12-17T02:59:48Z Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity Muataz Hameed Salih, Al Doori, Dr. The condition that drives a system to complete the processing of a number of functions within a given amount of time is called the real-time system. A projective missile system’s processing platforms face two major issues: high cost and structureal complexity. The system structure’s complexity is a result of various reasons that include the mechanism utilised in the system in order to perform the system functionality. This mechanism can lead to delays in data processing because various factors, such as the synchronisation of the system modules’ signals, the processing unit’s architecture, and the unit’s computational power. In order to lessen system complexity and system cost, true parallelism mechanism is applied over the embedded system, along with a concurrent structure. The FPGA platform (DE1-SoC) was used as the implementation environment for this system. This led to an enriched implemented system that had low costs. Furthermore, the system complexity is lessened since the system uses a concurrent structure. Some of the modules that are closely related to the system are implemented to support main processing module. In this system, the signals covered were in four directions. The total logic element was (5032) and total registers was (5180). The Phase Locked Loop up to (1.6) GHz was manipulated in order to allow the system cover a wide spectrum of signals with high accuracy of computing process. Furthermore, the laser projective frequency jamming system is capable of processing multiple frequencies at a time. The implementation was able to obtain acceptable levels of throughput and it also lowered the complexity. Furthermore, the structural design methodology also makes it possible for the embedded concurrent computing architecture to be scalable while the entire system grows. Universiti Malaysia Perlis (UniMAP) Thesis en http://dspace.unimap.edu.my:80/xmlui/handle/123456789/72440 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/3/license.txt 8a4605be74aa9ea9d79846c1fba20a33 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/1/Page%201-24.pdf 2c8f5e1a5d5e8f72de2d2919c2c75775 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/2/Full%20text.pdf 640e0fc73812a764ce85fad4e4f801d4 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/4/Hussein%20Ibrahim.pdf 621171ca0098c58540fb1d52a1dce15c Universiti Malaysia Perlis (UniMAP) Embedded computer systems Field programmable gate arrays Embedded system School of Computer and Communication Engineering
institution	Universiti Malaysia Perlis
collection	UniMAP Institutional Repository
language	English
advisor	Muataz Hameed Salih, Al Doori, Dr.
topic	Embedded computer systems Field programmable gate arrays Embedded system
spellingShingle	Embedded computer systems Field programmable gate arrays Embedded system Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
description	The condition that drives a system to complete the processing of a number of functions within a given amount of time is called the real-time system. A projective missile system’s processing platforms face two major issues: high cost and structureal complexity. The system structure’s complexity is a result of various reasons that include the mechanism utilised in the system in order to perform the system functionality. This mechanism can lead to delays in data processing because various factors, such as the synchronisation of the system modules’ signals, the processing unit’s architecture, and the unit’s computational power. In order to lessen system complexity and system cost, true parallelism mechanism is applied over the embedded system, along with a concurrent structure. The FPGA platform (DE1-SoC) was used as the implementation environment for this system. This led to an enriched implemented system that had low costs. Furthermore, the system complexity is lessened since the system uses a concurrent structure. Some of the modules that are closely related to the system are implemented to support main processing module. In this system, the signals covered were in four directions. The total logic element was (5032) and total registers was (5180). The Phase Locked Loop up to (1.6) GHz was manipulated in order to allow the system cover a wide spectrum of signals with high accuracy of computing process. Furthermore, the laser projective frequency jamming system is capable of processing multiple frequencies at a time. The implementation was able to obtain acceptable levels of throughput and it also lowered the complexity. Furthermore, the structural design methodology also makes it possible for the embedded concurrent computing architecture to be scalable while the entire system grows.
format	Thesis
title	Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_short	Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_full	Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_fullStr	Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_full_unstemmed	Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_sort	design and implementation of embedded true parallelism jammer system using fgpa-soc for low design complexity
granting_institution	Universiti Malaysia Perlis (UniMAP)
granting_department	School of Computer and Communication Engineering
url	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/72440/4/Hussein%20Ibrahim.pdf
_version_	1747836867338829824

Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity

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