Junctionless transistors: parametric study with conventional doping in MOSFETS
The advancement of today technologies has been aggressively developed as the needs of current technology that becoming competitive and demanding to accommodate human lifestyle. The electronic gadgets drive the market with the requirements to provide efficient chip functionality at higher speed and e...
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| Format: | Thesis |
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| Language: | English |
| Subjects: | |
| Online Access: | http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77894/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77894/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77894/4/Nurul%20Huda.pdf |
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| Summary: | The advancement of today technologies has been aggressively developed as the needs of current technology that becoming competitive and demanding to accommodate human lifestyle. The electronic gadgets drive the market with the requirements to provide efficient chip functionality at higher speed and extra functionality. This has become more challenging as the transistor density and performance are aggressively increasing. Thus, continuous downscaling of the conventional transistor will lead to severe short-channel effect (SCE), and one of the solutions is a ultra-shallow junction. Ultra-shallow junction is very challenging as it increases in fabrication cost and difficulty in the fabrication process. In this study, the channel, drain, and source have the same type of doping where the ultra-shallow junction has been eliminated. Hence, it is called junctionless. There will
be no diffusion will take place where it will remove the high cost for ultrafast annealing
techniques. Besides that, it allows the transistor to be fabricated with a shorter channel if
the gradient of the doping concentration is zero between drain and channel or source and
channel. This operation principle of the junctionless transistor is investigated through
numerical simulations using technology computer aided design (TCAD) simulation tools.
Firstly, the device performance of 3-Dimensional (3D) silicon-on-insulator (SOI)
junctionless transistor (JLT) with 100 and 10 nm gate lengths, have been compared to the
3D SOI junction transistor (JT) with the same gate length. In order to achieve full
depletion, the parameters such as metal gate workfunction, doping concentration, drain
bias, and dimension are considered in the simulation process. The digital figure-of-merits
characteristics such as threshold voltage (VTH), on-current, subthreshold slope, and draininduced-
barrier-lowering are the main parameters that have been investigated. Following
next is the characterization on the analog and radio frequency (RF) figures-of-merit.
Based on the simulations, 1) the designated JLT device is more suitable to the higher gate
workfunction of more than 5.0 eV whereas the designated JT device is more suitable with
mid-gap values of gate workfunction of 4.6 eV. 2) the JLT transistor requires high gate
work-function to have control over the channel. 3) the JT device is less sensitive to the
variation of silicon body thickness (TSi) and width (WSi) compared to JLT. Lastly, the
device performance on analog and RF figures of merit shows that no significant different
between JLT and JT with the latter case shows slightly better performance, related to
lower gate-to-gate capacitance (Cgg). |
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