Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening...
محفوظ في:
| التنسيق: | أطروحة |
|---|---|
| اللغة: | English |
| الموضوعات: | |
| الوصول للمادة أونلاين: | http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/4/Noraini%20Othman.pdf |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| الملخص: | The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching
the end of the technology roadmap due to worsening performance variability and shortchannel
effects (SCEs). One of the contenders anticipated to replace the current transistor architecture is planar ultra-thin body and BOX (UTBB) SOI MOSFET. The advantage of the thin-body SOI structure lies in its simple planar process which is fully
compatible with the bulk silicon CMOS flow. In this research work, a particular
attention is being given to the performance of UTBB SOI MOSFETs with its thin BOX
in improving electrostatics behaviour namely of drain-induced barrier lowering (DIBL)
of the thin-body as compared to thick BOX (UTB) SOI transistors for extending CMOS
scalability. Subsequently, UTBB with different ground plane (GP) architectures and
gate configurations (i.e. single-gate (SG) vs double-gate (DG)) are extensively studied
through numerical simulations as possible candidates for the continuation of Moore‟s
Law. In-depth study of the digital and analog/RF figure-of-merit (FoM) are carried out
in a wide range of frequency (from 0.01 Hz to 100 GHz) in correlation with device
operation mechanisms. It is discovered that an innovative GP formation made of
localized GP of p-type in the substrate underneath the channel (referred herein
throughout the thesis as GP-B) effectively suppress substrate depletion effects and
shows better immunity against SCEs from the digital analysis viewpoint. Further
improvements in the immunity against SCEs can be achieved in DG configurations
where the impact of different GP architectures is amplified as compared to SG. Even
though the use of DG configurations provides superior digital performance, lower
current gain cut-off frequency (ft) values are produced than SG in the analog domain
due to an increase of gate-to-gate capacitances (Cgg). Therefore, careful selections and
trade-offs are needed when selecting a particular device structure where the results
obtained in this research work contribute to the identifications of GP architectures and
gate configurations (SG or DG) that can be adopted in device design to suit specific
applications of either digital or RF. |
|---|