Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS

The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening...

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Format:	Thesis
Language:	English
Subjects:	Metal oxide semiconductors Complementary Electric insulators and insulation Metal oxide semiconductor field-effect transistors Silicon-on-insulator (SOI)
Online Access:	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/4/Noraini%20Othman.pdf
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spelling	my-unimap-779982023-03-06T04:19:57Z Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS Mohd Khairuddin, Md Arshad, Assoc. Prof. Ir. Dr. The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening performance variability and shortchannel effects (SCEs). One of the contenders anticipated to replace the current transistor architecture is planar ultra-thin body and BOX (UTBB) SOI MOSFET. The advantage of the thin-body SOI structure lies in its simple planar process which is fully compatible with the bulk silicon CMOS flow. In this research work, a particular attention is being given to the performance of UTBB SOI MOSFETs with its thin BOX in improving electrostatics behaviour namely of drain-induced barrier lowering (DIBL) of the thin-body as compared to thick BOX (UTB) SOI transistors for extending CMOS scalability. Subsequently, UTBB with different ground plane (GP) architectures and gate configurations (i.e. single-gate (SG) vs double-gate (DG)) are extensively studied through numerical simulations as possible candidates for the continuation of Moore‟s Law. In-depth study of the digital and analog/RF figure-of-merit (FoM) are carried out in a wide range of frequency (from 0.01 Hz to 100 GHz) in correlation with device operation mechanisms. It is discovered that an innovative GP formation made of localized GP of p-type in the substrate underneath the channel (referred herein throughout the thesis as GP-B) effectively suppress substrate depletion effects and shows better immunity against SCEs from the digital analysis viewpoint. Further improvements in the immunity against SCEs can be achieved in DG configurations where the impact of different GP architectures is amplified as compared to SG. Even though the use of DG configurations provides superior digital performance, lower current gain cut-off frequency (ft) values are produced than SG in the analog domain due to an increase of gate-to-gate capacitances (Cgg). Therefore, careful selections and trade-offs are needed when selecting a particular device structure where the results obtained in this research work contribute to the identifications of GP architectures and gate configurations (SG or DG) that can be adopted in device design to suit specific applications of either digital or RF. Universiti Malaysia Perlis (UniMAP) Thesis en http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77998 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/3/license.txt 8a4605be74aa9ea9d79846c1fba20a33 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/1/Page%201-24.pdf b69bd6ab6a1b0d5435267814aafb5469 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/2/Full%20text.pdf fdbfc4a229214c0f5c8c293ffc6c9f83 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/4/Noraini%20Othman.pdf 4de15a88dc2322a254a2ecd668d6b828 Universiti Malaysia Perlis (UniMAP) Metal oxide semiconductors, Complementary Electric insulators and insulation Metal oxide semiconductor field-effect transistors Silicon-on-insulator (SOI) School of Microelectronic Engineering
institution	Universiti Malaysia Perlis
collection	UniMAP Institutional Repository
language	English
advisor	Mohd Khairuddin, Md Arshad, Assoc. Prof. Ir. Dr.
topic	Metal oxide semiconductors Complementary Electric insulators and insulation Metal oxide semiconductor field-effect transistors Silicon-on-insulator (SOI)
spellingShingle	Metal oxide semiconductors Complementary Electric insulators and insulation Metal oxide semiconductor field-effect transistors Silicon-on-insulator (SOI) Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
description	The downscaling of transistors enables an increased in transistor density, faster switching speeds and greater complexity with no increase in power consumption. However, the scaling of the conventional planar MOS transistors appears to be reaching the end of the technology roadmap due to worsening performance variability and shortchannel effects (SCEs). One of the contenders anticipated to replace the current transistor architecture is planar ultra-thin body and BOX (UTBB) SOI MOSFET. The advantage of the thin-body SOI structure lies in its simple planar process which is fully compatible with the bulk silicon CMOS flow. In this research work, a particular attention is being given to the performance of UTBB SOI MOSFETs with its thin BOX in improving electrostatics behaviour namely of drain-induced barrier lowering (DIBL) of the thin-body as compared to thick BOX (UTB) SOI transistors for extending CMOS scalability. Subsequently, UTBB with different ground plane (GP) architectures and gate configurations (i.e. single-gate (SG) vs double-gate (DG)) are extensively studied through numerical simulations as possible candidates for the continuation of Moore‟s Law. In-depth study of the digital and analog/RF figure-of-merit (FoM) are carried out in a wide range of frequency (from 0.01 Hz to 100 GHz) in correlation with device operation mechanisms. It is discovered that an innovative GP formation made of localized GP of p-type in the substrate underneath the channel (referred herein throughout the thesis as GP-B) effectively suppress substrate depletion effects and shows better immunity against SCEs from the digital analysis viewpoint. Further improvements in the immunity against SCEs can be achieved in DG configurations where the impact of different GP architectures is amplified as compared to SG. Even though the use of DG configurations provides superior digital performance, lower current gain cut-off frequency (ft) values are produced than SG in the analog domain due to an increase of gate-to-gate capacitances (Cgg). Therefore, careful selections and trade-offs are needed when selecting a particular device structure where the results obtained in this research work contribute to the identifications of GP architectures and gate configurations (SG or DG) that can be adopted in device design to suit specific applications of either digital or RF.
format	Thesis
title	Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
title_short	Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
title_full	Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
title_fullStr	Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
title_full_unstemmed	Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS
title_sort	numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of soi mosfets
granting_institution	Universiti Malaysia Perlis (UniMAP)
granting_department	School of Microelectronic Engineering
url	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/1/Page%201-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/2/Full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/77998/4/Noraini%20Othman.pdf
_version_	1776104259080683520

Numerical simulations of innovative ground plane and double-gate configurations in thin-body and -buried oxide of SOI MOSFETS

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