Development of Test Procedure For CMOS Operational Amplifier Application Circuits

The integrated circuit (IC) is an ultra-small and fragile electrical system. A chip is basically an IC placed in a protective black plastic casing. The only contact the outside world has with the IC is through the chips input-output and power supply pins. ICs are also prone to damage and to locat...

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Main Author:	Abdul Halin, Izhal
Format:	Thesis
Language:	English English
Published:	2002
Subjects:	Amplifiers (Electronics) Circuits training
Online Access:	http://psasir.upm.edu.my/id/eprint/10476/1/FK_2002_8.pdf
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spelling	my-upm-ir.104762024-04-01T08:12:27Z Development of Test Procedure For CMOS Operational Amplifier Application Circuits 2002-01 Abdul Halin, Izhal The integrated circuit (IC) is an ultra-small and fragile electrical system. A chip is basically an IC placed in a protective black plastic casing. The only contact the outside world has with the IC is through the chips input-output and power supply pins. ICs are also prone to damage and to locate damages inside a chip requires special probing techniques. These techniques are incorporated from the beginning of the design stage of a chip. Design for Testability (DFT) is a method applied to the design stage of chips such that electrical testing of the chips at the end of the production stage is greatly simplified. For a chip manufacturer, DFT helps cut production cost by shortening the time to test finished chips w hich eventually decreases the time to market the chip. Built-In Self Test (BIST) chips, an outcome of DFT, are ICs designed with extended circuitry dedicated to test its electrical behavior which eventually could inform a manufacturer w here damage has occurred. The testing circuitry inside a BIST chip is complimented by a test pattern, which is a special signal that executes the actual testing. The main objective of this study is to develop a test procedure to test CMOS Operational Amplifier (Op-Amp) application circuits. The focus in the development of the testing procedure is to find a suitable test pattern. The study conducted results in the success of developing the said test procedure. The development of the test procedure is aided by a powerful computer software from Tanner Research Inc. called Tanner Tools. It is used for circuit simulation and development of a mask layout for an Op-Amp. The major findings of this thesis is that a faulty Op-Amp application circuit behaves differently from a faultless Op-Amp application circuit. From this finding a test pattern can be derived by comparing between faulty and faultless Op-Amp application circuit behavior through simulation. The only disadvantage of the test pattern is that it could only detect damages in the Op-Amp if the damages occurs only one at any given time. Thus it can be argued that in relation to DFT for an Op-Amp application circuit, it is not impossible for damages to be pin-pointed using the developed procedure. Amplifiers (Electronics) Circuits training 2002-01 Thesis http://psasir.upm.edu.my/id/eprint/10476/ http://psasir.upm.edu.my/id/eprint/10476/1/FK_2002_8.pdf text en public masters Universiti Putra Malaysia Amplifiers (Electronics) Circuits training Faculty of Engineering Suparjo, Bambang Sunaryo English
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English English
advisor	Suparjo, Bambang Sunaryo
topic	Amplifiers (Electronics) Circuits training
spellingShingle	Amplifiers (Electronics) Circuits training Abdul Halin, Izhal Development of Test Procedure For CMOS Operational Amplifier Application Circuits
description	The integrated circuit (IC) is an ultra-small and fragile electrical system. A chip is basically an IC placed in a protective black plastic casing. The only contact the outside world has with the IC is through the chips input-output and power supply pins. ICs are also prone to damage and to locate damages inside a chip requires special probing techniques. These techniques are incorporated from the beginning of the design stage of a chip. Design for Testability (DFT) is a method applied to the design stage of chips such that electrical testing of the chips at the end of the production stage is greatly simplified. For a chip manufacturer, DFT helps cut production cost by shortening the time to test finished chips w hich eventually decreases the time to market the chip. Built-In Self Test (BIST) chips, an outcome of DFT, are ICs designed with extended circuitry dedicated to test its electrical behavior which eventually could inform a manufacturer w here damage has occurred. The testing circuitry inside a BIST chip is complimented by a test pattern, which is a special signal that executes the actual testing. The main objective of this study is to develop a test procedure to test CMOS Operational Amplifier (Op-Amp) application circuits. The focus in the development of the testing procedure is to find a suitable test pattern. The study conducted results in the success of developing the said test procedure. The development of the test procedure is aided by a powerful computer software from Tanner Research Inc. called Tanner Tools. It is used for circuit simulation and development of a mask layout for an Op-Amp. The major findings of this thesis is that a faulty Op-Amp application circuit behaves differently from a faultless Op-Amp application circuit. From this finding a test pattern can be derived by comparing between faulty and faultless Op-Amp application circuit behavior through simulation. The only disadvantage of the test pattern is that it could only detect damages in the Op-Amp if the damages occurs only one at any given time. Thus it can be argued that in relation to DFT for an Op-Amp application circuit, it is not impossible for damages to be pin-pointed using the developed procedure.
format	Thesis
qualification_level	Master's degree
author	Abdul Halin, Izhal
author_facet	Abdul Halin, Izhal
author_sort	Abdul Halin, Izhal
title	Development of Test Procedure For CMOS Operational Amplifier Application Circuits
title_short	Development of Test Procedure For CMOS Operational Amplifier Application Circuits
title_full	Development of Test Procedure For CMOS Operational Amplifier Application Circuits
title_fullStr	Development of Test Procedure For CMOS Operational Amplifier Application Circuits
title_full_unstemmed	Development of Test Procedure For CMOS Operational Amplifier Application Circuits
title_sort	development of test procedure for cmos operational amplifier application circuits
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2002
url	http://psasir.upm.edu.my/id/eprint/10476/1/FK_2002_8.pdf
_version_	1804888548938088448

Development of Test Procedure For CMOS Operational Amplifier Application Circuits

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