Design of High-Speed Multiplier with Optimised Builtinself-Test

Design of High-Speed Multiplier with Optimised Builtinself-Test

Current trend in Integrated Circuits (IC) implementation such as System-on-Chip has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Since the development of System-on-Chip, whi...

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書目詳細資料
主要作者:	Wan Hasan, Wan Zuha
格式:	Thesis
語言:	English English
出版:	2000
主題:	Multiplier (Economics)
在線閱讀:	http://psasir.upm.edu.my/id/eprint/10478/1/FK_2000_14.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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