Device Characterization of 0.8-µm CMOS Technology

The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia. In every technology development, characterization of the technology is always necessary to gauge its performance and reliability. This thesis i...

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Main Author:	Kooh, Roy Jinn Chye
Format:	Thesis
Language:	English English
Published:	2000
Subjects:	Metal oxide semiconductors Complementary Integrated circuits - Very large scale integration
Online Access:	http://psasir.upm.edu.my/id/eprint/10536/1/FK_2000_45_A.pdf
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id	my-upm-ir.10536
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spelling	my-upm-ir.105362011-05-04T03:11:24Z Device Characterization of 0.8-µm CMOS Technology 2000-05 Kooh, Roy Jinn Chye The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia. In every technology development, characterization of the technology is always necessary to gauge its performance and reliability. This thesis is a result of such work and the emphasis of the characterization is the devices of O.8-um CMOS technology. The main work of this thesis includes the effort taken to understand the technology, the design of test structures and the development of test methodology to qualify the O. 8-um CMOS technology. The test structures design includes the p-n junction, MOS enhancement transistor, thick oxide transistor and MOS capacitor. The p-n junction was designed specifically to investigate the breakdown voltage of the source/drain of NMOS and PMOS, which is a very important parameter in determining the reliability of the devices. MOS enhancement transistor characteristics were examined in detail with the NMOS and PMOS test structures. Typical I-V characteristics and some important device parameters were obtained from the I-V characterization. Two main issues, i.e. threshold voltage variation and off state leakage current were discussed in detail. Test methodologies for effective channel length determination (LEFF), Drain-Induced Barrier Lowering (DIBL), punchthrough and Gate-Induced Drain Leakage (GIDL) are among the important ones that were developed. The isolation issues for the devices were addressed using the thick oxide transistors to obtain the high field threshold voltage (VTF). The VIP is used as a measure to show the absence of parasitic FET near the operating voltage of 5V. The conventional MOS capacitor was also included as one of the test structures due to its simplicity and enormous amount of information that can be obtained. A detail capacitance-voltage (C-V) characterization was carried out using the Simultaneous Feedback Charge technique. Analysis includes the extraction of doping profiles, interface trap density (Dit) and some process information such as conductivity and gate oxide thickness (tox). The work has shown a tremendous effort being put to design test structures and characterize the O.8-um CMOS devices. The test structures which designs are based on its predecessor, the 1.0-um CMOS technology test structures, have proven to be reliable and capable. Based on the result analysis, it shows that the O.8-um CMOS devices have achieved a creditable performance and reliability. As a conclusion, this work have achieved its objective to design device test structures, develop the respective test methodology and to characterize the technology. Metal oxide semiconductors, Complementary Integrated circuits - Very large scale integration 2000-05 Thesis http://psasir.upm.edu.my/id/eprint/10536/ http://psasir.upm.edu.my/id/eprint/10536/1/FK_2000_45_A.pdf application/pdf en public masters Universiti Putra Malaysia Metal oxide semiconductors, Complementary Integrated circuits - Very large scale integration Faculty of Engineering English
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English English
topic	Metal oxide semiconductors Complementary Integrated circuits - Very large scale integration
spellingShingle	Metal oxide semiconductors Complementary Integrated circuits - Very large scale integration Kooh, Roy Jinn Chye Device Characterization of 0.8-µm CMOS Technology
description	The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia. In every technology development, characterization of the technology is always necessary to gauge its performance and reliability. This thesis is a result of such work and the emphasis of the characterization is the devices of O.8-um CMOS technology. The main work of this thesis includes the effort taken to understand the technology, the design of test structures and the development of test methodology to qualify the O. 8-um CMOS technology. The test structures design includes the p-n junction, MOS enhancement transistor, thick oxide transistor and MOS capacitor. The p-n junction was designed specifically to investigate the breakdown voltage of the source/drain of NMOS and PMOS, which is a very important parameter in determining the reliability of the devices. MOS enhancement transistor characteristics were examined in detail with the NMOS and PMOS test structures. Typical I-V characteristics and some important device parameters were obtained from the I-V characterization. Two main issues, i.e. threshold voltage variation and off state leakage current were discussed in detail. Test methodologies for effective channel length determination (LEFF), Drain-Induced Barrier Lowering (DIBL), punchthrough and Gate-Induced Drain Leakage (GIDL) are among the important ones that were developed. The isolation issues for the devices were addressed using the thick oxide transistors to obtain the high field threshold voltage (VTF). The VIP is used as a measure to show the absence of parasitic FET near the operating voltage of 5V. The conventional MOS capacitor was also included as one of the test structures due to its simplicity and enormous amount of information that can be obtained. A detail capacitance-voltage (C-V) characterization was carried out using the Simultaneous Feedback Charge technique. Analysis includes the extraction of doping profiles, interface trap density (Dit) and some process information such as conductivity and gate oxide thickness (tox). The work has shown a tremendous effort being put to design test structures and characterize the O.8-um CMOS devices. The test structures which designs are based on its predecessor, the 1.0-um CMOS technology test structures, have proven to be reliable and capable. Based on the result analysis, it shows that the O.8-um CMOS devices have achieved a creditable performance and reliability. As a conclusion, this work have achieved its objective to design device test structures, develop the respective test methodology and to characterize the technology.
format	Thesis
qualification_level	Master's degree
author	Kooh, Roy Jinn Chye
author_facet	Kooh, Roy Jinn Chye
author_sort	Kooh, Roy Jinn Chye
title	Device Characterization of 0.8-µm CMOS Technology
title_short	Device Characterization of 0.8-µm CMOS Technology
title_full	Device Characterization of 0.8-µm CMOS Technology
title_fullStr	Device Characterization of 0.8-µm CMOS Technology
title_full_unstemmed	Device Characterization of 0.8-µm CMOS Technology
title_sort	device characterization of 0.8-µm cmos technology
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2000
url	http://psasir.upm.edu.my/id/eprint/10536/1/FK_2000_45_A.pdf
_version_	1747811145260990464

Device Characterization of 0.8-µm CMOS Technology

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