An Efficient Architecture of 8-Bit CMOS Analog-To-Digital Converter
An 8-bit CMOS analog-to-digital converter (ADC) has been designed by using a more efficient architecture, which is known as the simplified multistep flash architecture. This architecture can ultimately reduce the number of comparators needed in an ADC. For the same resolutions, the full-flash archit...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 语言: | English English |
| 出版: |
2000
|
| 主题: | |
| 在线阅读: | http://psasir.upm.edu.my/id/eprint/10664/1/FK_2000_47.pdf |
| 标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
| 总结: | An 8-bit CMOS analog-to-digital converter (ADC) has been designed by using a more efficient architecture, which is known as the simplified multistep flash architecture. This architecture can ultimately reduce the number of comparators needed in an ADC. For the same resolutions, the full-flash architecture requires 255 comparators; the half-flash architecture requires 30 comparators, but the new architecture needs only six comparators. For conversion speed, the half-flash architecture has about half the speed of the fullflash architecture, but the comparator counts for the half-flash architecture is greatly reduced compared to the full-flash architecture. While, for the simplified
multistep flash architecture, even though the comparator counts is very much reduced compared to the half-flash architecture, but the conversion speed of the new architecture is still the same as that of the half-flash architecture. In order to design this new ADC, the entire architecture is divided into six separate parts. The suitable computer aids for designing and doing simulation are employed at the beginning of the design process. In this project, the integrated circuit design program from Tanner Research, Inc. is used for designing from the
system level to the layout level. The simulation results show that the conversion rate of this new architecture is 111 kHz, while the differential non-linearity (DNL) and integral non-linearity (INL) of this architecture are both ± 1.19 LSB (least significant bit). This is due to the elimination of three digital codes of the conversion system. By ignoring these three missing codes, the new ADC is estimated to have not more than ±1.00 LSB of DNL and INL values. The mask layout diagram that is used for fabrication purpose is also successfully developed in this project. Although, the simulation results from the layout diagram indicate the system has lower accuracy compared to the expected results from the schematics, the conversion from an analog voltage to eight digital bits, is successfully achieved. The full-custom approach is chosen in
designing the layouts because it provides complete design freedom to the designer. |
|---|