An Efficient Architecture of 8-Bit CMOS Analog-To-Digital Converter
An 8-bit CMOS analog-to-digital converter (ADC) has been designed by using a more efficient architecture, which is known as the simplified multistep flash architecture. This architecture can ultimately reduce the number of comparators needed in an ADC. For the same resolutions, the full-flash archit...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English English |
| 出版: |
2000
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| 主題: | |
| 在線閱讀: | http://psasir.upm.edu.my/id/eprint/10664/1/FK_2000_47.pdf |
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