Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform well in digital signal processing-intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms simultan...

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Main Author:	Lee, Lini @ Lini Lee
Format:	Thesis
Language:	English English
Published:	2001
Subjects:	Digital electronics Architecture and technology
Online Access:	http://psasir.upm.edu.my/id/eprint/11027/1/FK_2001_42_A.pdf
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id	my-upm-ir.11027
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spelling	my-upm-ir.110272011-07-19T03:20:53Z Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture 2001-03 Lee, Lini @ Lini Lee Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform well in digital signal processing-intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing can be carried out and computational units can be integrated into the core with ease. In order to gain most benefit from the architecture, "Field Programmable Gate Array" (FPGA) technology can be used. FPGA technology is a technology, which gives the designer high flexibility in pDSP design. In order to fulfill the requirement of pDSP, "Very Long Instruction Word" (VLIW) architecture concept is used. Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. This flexibility of changing the data width or bit values is suitable in VLIW architecture approach. Based on the functional verification, the designed pDSP is able to perform mathematical operations required in signal processing. The speed of the operation is dependent on the size of the datapath as well as the type of FPGA chips. It has been shown that changing the data width or bit values in the VHDL source code of the subsystem can easily change the subsystems' sizes. Thus, the time for redesign is significandy shorten. Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). However, higher MIPS value can be achieved by using higher performance FPGAIPLO chip. Therefore, it is shown that VUW architecture concept is suitable for microprocessor architecture and the pDSP core is proven to be flexible in terms of size variation of the subsystems consequently the variation of the operation speed. Digital electronics Architecture and technology 2001-03 Thesis http://psasir.upm.edu.my/id/eprint/11027/ http://psasir.upm.edu.my/id/eprint/11027/1/FK_2001_42_A.pdf application/pdf en public masters Universiti Putra Malaysia Digital electronics Architecture and technology Faculty of Engineering English
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English English
topic	Digital electronics Architecture and technology
spellingShingle	Digital electronics Architecture and technology Lee, Lini @ Lini Lee Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
description	Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform well in digital signal processing-intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing can be carried out and computational units can be integrated into the core with ease. In order to gain most benefit from the architecture, "Field Programmable Gate Array" (FPGA) technology can be used. FPGA technology is a technology, which gives the designer high flexibility in pDSP design. In order to fulfill the requirement of pDSP, "Very Long Instruction Word" (VLIW) architecture concept is used. Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. This flexibility of changing the data width or bit values is suitable in VLIW architecture approach. Based on the functional verification, the designed pDSP is able to perform mathematical operations required in signal processing. The speed of the operation is dependent on the size of the datapath as well as the type of FPGA chips. It has been shown that changing the data width or bit values in the VHDL source code of the subsystem can easily change the subsystems' sizes. Thus, the time for redesign is significandy shorten. Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). However, higher MIPS value can be achieved by using higher performance FPGAIPLO chip. Therefore, it is shown that VUW architecture concept is suitable for microprocessor architecture and the pDSP core is proven to be flexible in terms of size variation of the subsystems consequently the variation of the operation speed.
format	Thesis
qualification_level	Master's degree
author	Lee, Lini @ Lini Lee
author_facet	Lee, Lini @ Lini Lee
author_sort	Lee, Lini @ Lini Lee
title	Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
title_short	Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
title_full	Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
title_fullStr	Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
title_full_unstemmed	Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture
title_sort	digital signal processor (dsp) design using very long instruction word (vliw) architecture
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2001
url	http://psasir.upm.edu.my/id/eprint/11027/1/FK_2001_42_A.pdf
_version_	1747811196040380416

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

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