Design of Asynchronous Processor

There has been a resurgence of interest in asynchronous design recently. The renewed interest in asynchronous design results from its potential to address the problem faced by the synchronous design methodology. In asynchronous methodology, there is no global clock controlling the synchronization o...

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主要作者:	Puah, Wei Boo
格式:	Thesis
语言:	English English
出版:	2001
主题:	Asynchronous transfer mode
在线阅读:	http://psasir.upm.edu.my/id/eprint/11176/1/FK_2001_60.pdf
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id	my-upm-ir.11176
record_format	uketd_dc
spelling	my-upm-ir.111762024-05-31T00:53:04Z Design of Asynchronous Processor 2001-07 Puah, Wei Boo There has been a resurgence of interest in asynchronous design recently. The renewed interest in asynchronous design results from its potential to address the problem faced by the synchronous design methodology. In asynchronous methodology, there is no global clock controlling the synchronization of a circuit; instead, the data communication between each functional unit is completed through local request-acknowledge handshake protocol. The growth in demand of high performance portable systems has accelerated asynchronous logic design technique which can offers better performance and lower power consumption especially in the development of the asynchronous processor for mobile and portable application. In this thesis, the design and verification of an 8-bit asynchronous pipelined processor is presented. The developed asynchronous processor is based on Harvard architecture and uses Reduced Instruction Set Computer (RISC) instruction set architecture. 24 instructions are supported by the processor including register, memory, branch and jump operations. The processor has three-stage pipelining i.e. fetch, decode and execution pipeline. Micropipelines framework with 2-phase signalling protocol and bundled-data approach is employed in designing complex and powerful asynchronous control circuits for the processor. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to design and construct all parts of the asynchronous processor. Simulation, synthesis and verification of the processor are carried out using MAX +PLUS II software. The simulation results have demonstrated that the developed 8-bit asynchronous RISC processor is working correctly using current Field Programmable Gate Array (FPGA) technology. This processor employed 903 logic cells and has 6144 memory bits for instruction and data memory. Each of the processor subsystem can operates at different cycle time, thus enable an asynchronous processor achieving 11.95MHz average speed performance. Asynchronous transfer mode 2001-07 Thesis http://psasir.upm.edu.my/id/eprint/11176/ http://psasir.upm.edu.my/id/eprint/11176/1/FK_2001_60.pdf text en public masters Universiti Putra Malaysia Asynchronous transfer mode Faculty of Engineering Suparjo, Bambang Sunaryo English
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English English
advisor	Suparjo, Bambang Sunaryo
topic	Asynchronous transfer mode
spellingShingle	Asynchronous transfer mode Puah, Wei Boo Design of Asynchronous Processor
description	There has been a resurgence of interest in asynchronous design recently. The renewed interest in asynchronous design results from its potential to address the problem faced by the synchronous design methodology. In asynchronous methodology, there is no global clock controlling the synchronization of a circuit; instead, the data communication between each functional unit is completed through local request-acknowledge handshake protocol. The growth in demand of high performance portable systems has accelerated asynchronous logic design technique which can offers better performance and lower power consumption especially in the development of the asynchronous processor for mobile and portable application. In this thesis, the design and verification of an 8-bit asynchronous pipelined processor is presented. The developed asynchronous processor is based on Harvard architecture and uses Reduced Instruction Set Computer (RISC) instruction set architecture. 24 instructions are supported by the processor including register, memory, branch and jump operations. The processor has three-stage pipelining i.e. fetch, decode and execution pipeline. Micropipelines framework with 2-phase signalling protocol and bundled-data approach is employed in designing complex and powerful asynchronous control circuits for the processor. Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to design and construct all parts of the asynchronous processor. Simulation, synthesis and verification of the processor are carried out using MAX +PLUS II software. The simulation results have demonstrated that the developed 8-bit asynchronous RISC processor is working correctly using current Field Programmable Gate Array (FPGA) technology. This processor employed 903 logic cells and has 6144 memory bits for instruction and data memory. Each of the processor subsystem can operates at different cycle time, thus enable an asynchronous processor achieving 11.95MHz average speed performance.
format	Thesis
qualification_level	Master's degree
author	Puah, Wei Boo
author_facet	Puah, Wei Boo
author_sort	Puah, Wei Boo
title	Design of Asynchronous Processor
title_short	Design of Asynchronous Processor
title_full	Design of Asynchronous Processor
title_fullStr	Design of Asynchronous Processor
title_full_unstemmed	Design of Asynchronous Processor
title_sort	design of asynchronous processor
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2001
url	http://psasir.upm.edu.my/id/eprint/11176/1/FK_2001_60.pdf
_version_	1804888620358696960

Design of Asynchronous Processor

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