Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption

Microprocessors are widely used in various applications. One of the application is in the area of data security where data are encrypted and decrypted before and after transfer via communication channel. The microprocessor design can be categorized into two types, which are synchronous and asynch...

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Main Author:	Pang, Wai Leong
Format:	Thesis
Language:	English English
Published:	2003
Subjects:	Microprocessor Asynchronous transfer mode
Online Access:	http://psasir.upm.edu.my/id/eprint/12210/1/FK_2003_48.pdf
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id	my-upm-ir.12210
record_format	uketd_dc
spelling	my-upm-ir.122102024-07-04T09:02:50Z Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption 2003-09 Pang, Wai Leong Microprocessors are widely used in various applications. One of the application is in the area of data security where data are encrypted and decrypted before and after transfer via communication channel. The microprocessor design can be categorized into two types, which are synchronous and asynchronous processors. The asynchronous processor may offer better speed improvement because it is self-timed where a control circuit will generate enable signals for all instruction executions based on the request and acknowledgement signals. Unlike the asynchronous design, synchronous design requires global clock. The clock must be long enough to accommodate the worst-case delay. In this work, an 8-bit asynchronous processor is designed based on a synchronous RISC pipe lined processor architecture. The synchronous processor consists of three stages. They are instruction fetch stage, instruction decode stage and execution stage. The reduce instruction set computer (RISC) architecture is used to minimize the instruction and to perform specific operation. To design the asynchronous processor, an asynchronous control circuit is added to synchronous design. The asynchronous control circuit is designed based on handshake protocol. Both the synchronous and asynchronous designs are applied fully using VHDL. The MAX+PLUS II is used as the simulation tools to design and for design verification. The UP1 education board that contains the FLEX10K chip is used to observe the hardware operation. The asynchronous processor was successfully designed with higher million instructions per second (MIPS) and higher operation frequency as compared to synchronous processor. The asynchronous processor has 10.772 MIPS and operated under frequency of 11. 16MHz. The asynchronous processor design consumed 63% of the total logic cells in FLEX10K chip. The processor fits in FLEX10K and provides extra spaces for future expansion. Microprocessor Asynchronous transfer mode 2003-09 Thesis http://psasir.upm.edu.my/id/eprint/12210/ http://psasir.upm.edu.my/id/eprint/12210/1/FK_2003_48.pdf text en public masters Universiti Putra Malaysia Microprocessor Asynchronous transfer mode Faculty of Engineering Mohd. Sidek, Roslina English
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English English
advisor	Mohd. Sidek, Roslina
topic	Microprocessor Asynchronous transfer mode
spellingShingle	Microprocessor Asynchronous transfer mode Pang, Wai Leong Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
description	Microprocessors are widely used in various applications. One of the application is in the area of data security where data are encrypted and decrypted before and after transfer via communication channel. The microprocessor design can be categorized into two types, which are synchronous and asynchronous processors. The asynchronous processor may offer better speed improvement because it is self-timed where a control circuit will generate enable signals for all instruction executions based on the request and acknowledgement signals. Unlike the asynchronous design, synchronous design requires global clock. The clock must be long enough to accommodate the worst-case delay. In this work, an 8-bit asynchronous processor is designed based on a synchronous RISC pipe lined processor architecture. The synchronous processor consists of three stages. They are instruction fetch stage, instruction decode stage and execution stage. The reduce instruction set computer (RISC) architecture is used to minimize the instruction and to perform specific operation. To design the asynchronous processor, an asynchronous control circuit is added to synchronous design. The asynchronous control circuit is designed based on handshake protocol. Both the synchronous and asynchronous designs are applied fully using VHDL. The MAX+PLUS II is used as the simulation tools to design and for design verification. The UP1 education board that contains the FLEX10K chip is used to observe the hardware operation. The asynchronous processor was successfully designed with higher million instructions per second (MIPS) and higher operation frequency as compared to synchronous processor. The asynchronous processor has 10.772 MIPS and operated under frequency of 11. 16MHz. The asynchronous processor design consumed 63% of the total logic cells in FLEX10K chip. The processor fits in FLEX10K and provides extra spaces for future expansion.
format	Thesis
qualification_level	Master's degree
author	Pang, Wai Leong
author_facet	Pang, Wai Leong
author_sort	Pang, Wai Leong
title	Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
title_short	Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
title_full	Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
title_fullStr	Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
title_full_unstemmed	Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption
title_sort	development of an 8-bit fpga-based asynchronous risc pipelined processor for data encryption
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2003
url	http://psasir.upm.edu.my/id/eprint/12210/1/FK_2003_48.pdf
_version_	1804888698164084736

Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption

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