Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip

With the continuous downscaling in semiconductor technology more blocks are being integrated in a single chip. Network on Chip (NoC) represents the main solution for the increased on chip communication complexity. One of the major challenges in NoC is the communication reliability due to the small f...

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Main Author:	Flayyih, Wameedh Nazar
Format:	Thesis
Language:	English
Published:	2014
Subjects:	Network on a chip
Online Access:	http://psasir.upm.edu.my/id/eprint/47958/1/FK%202014%209R.pdf
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spelling	my-upm-ir.479582017-02-21T08:10:19Z Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip 2014-08 Flayyih, Wameedh Nazar With the continuous downscaling in semiconductor technology more blocks are being integrated in a single chip. Network on Chip (NoC) represents the main solution for the increased on chip communication complexity. One of the major challenges in NoC is the communication reliability due to the small feature sizes, high operating frequency and low operating voltage of the chips. Achieving reliable operation under the influence of deep-submicron noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this work, new joint coding schemes are proposed to provide high level of protection from errors and simultaneously reduce the crosstalk induced bus delay. The proposed coding schemes are based on wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This Duplicated Two-Dimensional Parities (DTDP) coding provides high Hamming distance allowing high error protection capability. In addition, the duplication technique addresses crosstalk delay effects allowing higher bus frequency operation. The high error protection capability enables the reduction of wires operating voltage while maintaining the target reliability level, leading to power/energy savings. For a given Hamming distance, providing only error detection without correction provides the highest possible protection. Accordingly, the first proposed coding scheme is based on automatic repeat request (ARQ) policy providing up to seven errors detection, thus named DTDP-7ED. On the other hand, the second proposed coding scheme is based on hybrid ARQ (HARQ) policy. Single error correction capability is added to reduce the retransmission probability which comes on the cost of reduced error detection capability, resulting in single error correction and six error detection (DTDP-SEC6ED). The two proposed schemes allow for higher reduction in voltage swing as compared to other joint coding schemes which reflects into higher power savings. Since DTDP-7ED has the highest error detection which results into the lowest voltage swing, it achieved the highest power savings. On the other hand, DTDP-SEC6ED achieved lower energy consumption and higher performance. We also propose a coding scheme that jointly provides crosstalk delay reduction and adaptable error protection according to noise severity. This was motivated by the inefficient energy consumption of traditional designs that constantly work assuming worst case noise scenario. The scheme works in one of three modes by duplicating the data bits, the data bits and one-dimensional parities, or the data bits and two dimensional parities at low, intermediate, and high noise conditions respectively. The maximum protection mode achieves 51.1% energy savings over Duplicate Add Parity (DAP) coding scheme. This energy savings is increased to 59.5% and 63.0% at intermediate and low protection modes respectively. This comes with a comparable area and maximum frequency compared to other similar coding schemes. Network on a chip 2014-08 Thesis http://psasir.upm.edu.my/id/eprint/47958/ http://psasir.upm.edu.my/id/eprint/47958/1/FK%202014%209R.pdf application/pdf en public phd doctoral Universiti Putra Malaysia Network on a chip
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English
topic	Network on a chip
spellingShingle	Network on a chip Flayyih, Wameedh Nazar Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
description	With the continuous downscaling in semiconductor technology more blocks are being integrated in a single chip. Network on Chip (NoC) represents the main solution for the increased on chip communication complexity. One of the major challenges in NoC is the communication reliability due to the small feature sizes, high operating frequency and low operating voltage of the chips. Achieving reliable operation under the influence of deep-submicron noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this work, new joint coding schemes are proposed to provide high level of protection from errors and simultaneously reduce the crosstalk induced bus delay. The proposed coding schemes are based on wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This Duplicated Two-Dimensional Parities (DTDP) coding provides high Hamming distance allowing high error protection capability. In addition, the duplication technique addresses crosstalk delay effects allowing higher bus frequency operation. The high error protection capability enables the reduction of wires operating voltage while maintaining the target reliability level, leading to power/energy savings. For a given Hamming distance, providing only error detection without correction provides the highest possible protection. Accordingly, the first proposed coding scheme is based on automatic repeat request (ARQ) policy providing up to seven errors detection, thus named DTDP-7ED. On the other hand, the second proposed coding scheme is based on hybrid ARQ (HARQ) policy. Single error correction capability is added to reduce the retransmission probability which comes on the cost of reduced error detection capability, resulting in single error correction and six error detection (DTDP-SEC6ED). The two proposed schemes allow for higher reduction in voltage swing as compared to other joint coding schemes which reflects into higher power savings. Since DTDP-7ED has the highest error detection which results into the lowest voltage swing, it achieved the highest power savings. On the other hand, DTDP-SEC6ED achieved lower energy consumption and higher performance. We also propose a coding scheme that jointly provides crosstalk delay reduction and adaptable error protection according to noise severity. This was motivated by the inefficient energy consumption of traditional designs that constantly work assuming worst case noise scenario. The scheme works in one of three modes by duplicating the data bits, the data bits and one-dimensional parities, or the data bits and two dimensional parities at low, intermediate, and high noise conditions respectively. The maximum protection mode achieves 51.1% energy savings over Duplicate Add Parity (DAP) coding scheme. This energy savings is increased to 59.5% and 63.0% at intermediate and low protection modes respectively. This comes with a comparable area and maximum frequency compared to other similar coding schemes.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Flayyih, Wameedh Nazar
author_facet	Flayyih, Wameedh Nazar
author_sort	Flayyih, Wameedh Nazar
title	Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
title_short	Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
title_full	Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
title_fullStr	Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
title_full_unstemmed	Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
title_sort	crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
granting_institution	Universiti Putra Malaysia
publishDate	2014
url	http://psasir.upm.edu.my/id/eprint/47958/1/FK%202014%209R.pdf
_version_	1747811955344670720

Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip

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