Design and implementation of real data fast fourier transform processor on field programmable gates array

The Fast Fourier Transform (FFT) is an efficient method to achieve the Discrete Fourier Transform (DFT) with less number of operations. FFT utilizes the symmetry property in the DFT to calculate the output. For input length of N=2m, FFT requires only Nlog2N multiplications instead of the N2 multipli...

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Main Author:	Ahmed, Mohammed Kassim
Format:	Thesis
Language:	English
Published:	2015
Subjects:	Fourier transformations Field programmable gate arrays
Online Access:	http://psasir.upm.edu.my/id/eprint/56225/1/FK%202015%2039RR.pdf
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spelling	my-upm-ir.562252017-06-30T03:02:00Z Design and implementation of real data fast fourier transform processor on field programmable gates array 2015-07 Ahmed, Mohammed Kassim The Fast Fourier Transform (FFT) is an efficient method to achieve the Discrete Fourier Transform (DFT) with less number of operations. FFT utilizes the symmetry property in the DFT to calculate the output. For input length of N=2m, FFT requires only Nlog2N multiplications instead of the N2 multiplications needed for the DFT. Although FFT is mostly used to transform complex values into frequency domain, but still there are cases where the FFT inputs are only real values. In such cases, the transform will unnecessarily use higher power and area to calculate the output. In order to calculate the DFT efficiently, various FFT algorithms and architectures have been presented. So far, different approaches of achieving FFT for real-valued inputs has been discussed and implemented. However, to the best of author's knowledge, no work has been found so far making direct experimental comparison between these approaches. Therefore, and for accurate comparison, this study aims to investigate the most common algorithms of RFFT on the same device and resources used. In this work, the memorybased FFT processor, based on radix-4 FFT algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). In order to program the FPGA, Verilog Hardware Description Language (Verilog HDL) is used. The radix-4 FFT algorithm will be implemented for 64 and 256 points using both 8-bit and 16-bit input width. The results are compared and analyzed in terms of output accuracy and power consumption. Two main RFFT approaches are discussed in this work. The Butterfly approach is mainly based on cancelling the unnecessary operations while maintaining the same FFT size.The Formula approach, on the other hand, uses a half size complex FFT to perform the full size RFFT. The results show that for 64-points, the Butterfly approach requires 82.95% of the power required by the complex FFT. Similarly, the Formula approach required 83.63% to perform the FFT which is nearly equal to the power required by the butterfly approach. For 256-points, in contrast, the results show that the Formula approach requires only 72.1% of the power required by the complex FFT. This is notab fewer than the 76.62% required by the Butterfly approach. Additionally, the results show that the 8-bit input data width saves a lot of power with a slightly higher error rate compared to the 16-bit width. Therefore, unless high output accuracy is essential, the 8-bit can be efficiently adopted for FFT input. Fourier transformations Field programmable gate arrays 2015-07 Thesis http://psasir.upm.edu.my/id/eprint/56225/ http://psasir.upm.edu.my/id/eprint/56225/1/FK%202015%2039RR.pdf application/pdf en public masters Universiti Putra Malaysia Fourier transformations Field programmable gate arrays
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English
topic	Fourier transformations Field programmable gate arrays
spellingShingle	Fourier transformations Field programmable gate arrays Ahmed, Mohammed Kassim Design and implementation of real data fast fourier transform processor on field programmable gates array
description	The Fast Fourier Transform (FFT) is an efficient method to achieve the Discrete Fourier Transform (DFT) with less number of operations. FFT utilizes the symmetry property in the DFT to calculate the output. For input length of N=2m, FFT requires only Nlog2N multiplications instead of the N2 multiplications needed for the DFT. Although FFT is mostly used to transform complex values into frequency domain, but still there are cases where the FFT inputs are only real values. In such cases, the transform will unnecessarily use higher power and area to calculate the output. In order to calculate the DFT efficiently, various FFT algorithms and architectures have been presented. So far, different approaches of achieving FFT for real-valued inputs has been discussed and implemented. However, to the best of author's knowledge, no work has been found so far making direct experimental comparison between these approaches. Therefore, and for accurate comparison, this study aims to investigate the most common algorithms of RFFT on the same device and resources used. In this work, the memorybased FFT processor, based on radix-4 FFT algorithm is implemented on Cyclone II Field Programmable Gates Array (FPGA). In order to program the FPGA, Verilog Hardware Description Language (Verilog HDL) is used. The radix-4 FFT algorithm will be implemented for 64 and 256 points using both 8-bit and 16-bit input width. The results are compared and analyzed in terms of output accuracy and power consumption. Two main RFFT approaches are discussed in this work. The Butterfly approach is mainly based on cancelling the unnecessary operations while maintaining the same FFT size.The Formula approach, on the other hand, uses a half size complex FFT to perform the full size RFFT. The results show that for 64-points, the Butterfly approach requires 82.95% of the power required by the complex FFT. Similarly, the Formula approach required 83.63% to perform the FFT which is nearly equal to the power required by the butterfly approach. For 256-points, in contrast, the results show that the Formula approach requires only 72.1% of the power required by the complex FFT. This is notab fewer than the 76.62% required by the Butterfly approach. Additionally, the results show that the 8-bit input data width saves a lot of power with a slightly higher error rate compared to the 16-bit width. Therefore, unless high output accuracy is essential, the 8-bit can be efficiently adopted for FFT input.
format	Thesis
qualification_level	Master's degree
author	Ahmed, Mohammed Kassim
author_facet	Ahmed, Mohammed Kassim
author_sort	Ahmed, Mohammed Kassim
title	Design and implementation of real data fast fourier transform processor on field programmable gates array
title_short	Design and implementation of real data fast fourier transform processor on field programmable gates array
title_full	Design and implementation of real data fast fourier transform processor on field programmable gates array
title_fullStr	Design and implementation of real data fast fourier transform processor on field programmable gates array
title_full_unstemmed	Design and implementation of real data fast fourier transform processor on field programmable gates array
title_sort	design and implementation of real data fast fourier transform processor on field programmable gates array
granting_institution	Universiti Putra Malaysia
publishDate	2015
url	http://psasir.upm.edu.my/id/eprint/56225/1/FK%202015%2039RR.pdf
_version_	1747812128212910080

Design and implementation of real data fast fourier transform processor on field programmable gates array

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