On-chip communication system modeling approach for reability analysis focusing on functional failures
The advances in the process technology have shrunk the feature size which has paved the road to higher orders of integration in the recent years. Year by year, the number of components integrated into a single chip is growing. Resulted in larger number of interconnects, the communication between the...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2012
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| Subjects: | |
| Online Access: | http://psasir.upm.edu.my/id/eprint/59772/1/FK%202012%2095IR.pdf |
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| Summary: | The advances in the process technology have shrunk the feature size which has paved the road to higher orders of integration in the recent years. Year by year, the number of components integrated into a single chip is growing. Resulted in larger number of interconnects, the communication between these components is increasingly taking over critical system paths and frequently becomes the basis for performance holdup. Variations of communication and circuit-level techniques are proposed in the literature to facilitate the communication between the on-chip components. While improving communication reliability, power consumption and communication delay are the main concerns of such techniques, most of them are evaluated under unrealistic assumptions about the on-chip communication system. Therefore, the lack of a comprehensive approach for modeling on-chip communication systems is highlighted as the motivation behind this research. Based on that, a fast and accurate modeling approach inclusive of the impacts of significant contributors to the deep sub-micron noise as well as the
dynamic behavior of the receivers is proposed.
This research also investigates the tradeoff between accuracy and computational cost in crosstalk modeling as a part of the modeling approach which has critical impact on the total simulation precision and computational cost. Two algorithms are proposed to control the crosstalk simulation error while minimizing the required computational cost.An adaptive modeling window sizing method, along with an upper bound on the sampling error were applied to guarantee a high order of precision in simulating the crosstalk noise for an RLC interconnect model. The algorithms were verified and the resultsshow that minimum accuracy of 96% is maintained by applying the proposed crosstalk modeling approach while the number of required simulations is reduced by at least factor of 59% for modeling window sizes bigger than 3.
Finally, the significance of using a practical on-chip communication system model is demonstrated through applying the proposed modelling approach to study the impacts of different communication approaches and circuit-level modifications on the reliability performance focussing on functional failures. Using 4-PAM modulation as the signaling scheme together with three variations of Hamming block codes, the proposed on/off chip communicationsystem model is compared to AWGN model in terms of bit error ratio. The results confirm that application of simplistic on-chip communication system
models like AWGN or primitive crosstalk models leads to inaccurate evaluation of communication techniques while the proposed method is verified to offer a more
realistic platform. |
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