Deterministic Automatic Test Pattern Generation for Built-In Self Test System

With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly design...

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Main Author:	Mohammed Khalid, Muhammad Nazir
Format:	Thesis
Language:	English
Published:	2006
Subjects:	Automatic control System analysis
Online Access:	http://psasir.upm.edu.my/id/eprint/655/1/600530_FK_2006_53.pdf
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spelling	my-upm-ir.6552015-05-22T01:56:21Z Deterministic Automatic Test Pattern Generation for Built-In Self Test System 2006-03 Mohammed Khalid, Muhammad Nazir With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/subtractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost. Automatic control System analysis 2006-03 Thesis http://psasir.upm.edu.my/id/eprint/655/ http://psasir.upm.edu.my/id/eprint/655/1/600530_FK_2006_53.pdf application/pdf en public masters Universiti Putra Malaysia Automatic control System analysis Faculty of Engineering
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English
topic	Automatic control System analysis
spellingShingle	Automatic control System analysis Mohammed Khalid, Muhammad Nazir Deterministic Automatic Test Pattern Generation for Built-In Self Test System
description	With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/subtractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost.
format	Thesis
qualification_level	Master's degree
author	Mohammed Khalid, Muhammad Nazir
author_facet	Mohammed Khalid, Muhammad Nazir
author_sort	Mohammed Khalid, Muhammad Nazir
title	Deterministic Automatic Test Pattern Generation for Built-In Self Test System
title_short	Deterministic Automatic Test Pattern Generation for Built-In Self Test System
title_full	Deterministic Automatic Test Pattern Generation for Built-In Self Test System
title_fullStr	Deterministic Automatic Test Pattern Generation for Built-In Self Test System
title_full_unstemmed	Deterministic Automatic Test Pattern Generation for Built-In Self Test System
title_sort	deterministic automatic test pattern generation for built-in self test system
granting_institution	Universiti Putra Malaysia
granting_department	Faculty of Engineering
publishDate	2006
url	http://psasir.upm.edu.my/id/eprint/655/1/600530_FK_2006_53.pdf
_version_	1747810281728245760

Deterministic Automatic Test Pattern Generation for Built-In Self Test System

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