Design of Quaternary Logic Carry Look-Ahead Adder
In today's state-of-the-art VLSI technology, binary number system has been the choice for designing digital subsystems. Although technology development has made down scaling of devices possible, which in turn has resulted in a remarkable increase in density and functionality of VLSI systems...
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Format: | Thesis |
Language: | English English |
Published: |
2009
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Subjects: | |
Online Access: | http://psasir.upm.edu.my/id/eprint/7336/1/FK_2009_19a.pdf |
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Summary: | In today's state-of-the-art VLSI technology, binary number system has
been the choice for designing digital subsystems. Although technology
development has made down scaling of devices possible, which in turn has
resulted in a remarkable increase in density and functionality of VLSI
systems, there are also significant drawbacks associated to the
conventional binary number based system implementations.
As the number of devices in VLSI circuits increases to billion of transistors
in a chip area of , interconnection between the active devices both on
chip and outside of a chip becomes considerably complicated. In a typical
VLSI chip, about 70 percent of the chip area is occupied by
interconnections whereas just 10 percent of the chip area is devoted to the
devices and the remaining 20 percent is used for insulation.
mm2
In this situation, multiple valued logics have attracted a considerable
attention of researchers as a solution to overcome the above mentioned problem. Since fewer digits are required to represent a number in higher
radices than in the binary number system, multiple valued logic circuits
have the potential to minimize the number of interconnections.
This thesis presents voltage-mode quaternary (4-valued) logic carry lookahead
adder design using Silicon-On-Insulator (SOI) MOSFETs. The
choice of adder subsystem is made because addition operation is the most
frequently used operation in a general purpose system and in application
specific processors. Further more, the other operations like subtraction,
multiplication and division are based on addition operation of the arithmetic
unit. In this study, an efficient logic to realize 4-valued logic addition
operation is proposed. The presented method is in conjunction with binary
logic concepts and is easily developed for look-ahead logic. Following the
proposed method has resulted in logic circuits with shorter gate depth and
faster speed of operation as compared to what the other researchers have
proposed.
To meet the design requirements of the proposed low-voltage low-power
circuits, multiple threshold voltage SOI MOSFETs are used. This choice is
made because of their capability to operate at low power supply voltages
and their ability to remain at the adjusted threshold voltages while
presenting better subthreshold characteristics compared to the bulk
MOSFETs.
The proposed half and full adder blocks are divided into a few subblocks
which could be considered as primitive gates. Transistor-Resistor Logic is
used to implement each of them. Spice simulations have been performed
on the proposed logic subblocks and their transient behaviors have been studied. Finally, the propagation delay, power consumption and overall
performance of the proposed circuits are compared with other adder
circuits proposed by other researchers. The presented adder circuits in this
work have shown up to 58% reduction in critical propagation delay and
20% less power dissipation resulting in 64% reduction in power-delay
product in comparison with other reported work. When compared to the
binary logic carry look-ahead adder using the same technology (SOI),
54.39% improvement in power dissipation was achieved. |
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