Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology
Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because o...
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my-upm-ir.73572013-05-27T07:34:52Z Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology 2009-06 Alihasan, Wael A. Y. Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because of scaling properties of very large scale integration (VLSI) processes. This has allowed new generation of digital circuit to attain higher speed, more functionality per chip, low power dissipation, lower cost. Analog world, analog to digital converter (ADC) are used to convert the signal from analog to digital domain. For interfacing with DSP sample and hold (S/H) circuit is a key building block in, and is often used in front end of the ADCs to relax their timing requirement. The function of S/H circuit is to take samples to its input signal and hold these samples in its output for some period of time. The analog circuits in low voltage and low power have assumed great significance due to mixed-mode design required for modern electronic gadgets that demand portability and little power consumption. The mixed mode circuit has existence of both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not always true with analog circuits due to the constrains of device noise level and threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same substrate along with digital system and share same supply voltage, the operation of analog circuit in low voltage environment is essential. The objective of this research is to design a low-voltage, high-performance S/H circuit that will address the above problems. A typical switch capacitor S/H circuit needs amplifier, switches and capacitor. New amplifier have been designed by using the architecture of single stage fully differential folded cascode low voltage operation transconductance amplifier (OTA) which has high gain and speed; the gin boosting technique was used for purpose of increasing the gain of the OTA. This technique does not affect the speed of the single stage. The transmission gate switches using CMOS devices, which have higher linearity and higher speed over a single MOS switch, have been designed for use in the S/H circuit. The switches are operated by clock generator with two non overlapping clock signals having low rise and fall time offering low noise for the S/H circuit. The clock was designed with 77.17ps rise and fall time to reduce the errors of driving MOS switches which results in higher linearity. The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR) 65.7dB and SNR 70dB. 2009-06 Thesis http://psasir.upm.edu.my/id/eprint/7357/ http://psasir.upm.edu.my/id/eprint/7357/1/FK_2009_47a.pdf application/pdf en public masters Universiti Putra Malaysia Faculty of Engineering English |
| institution |
Universiti Putra Malaysia |
| collection |
PSAS Institutional Repository |
| language |
English English |
| topic |
|
| spellingShingle |
Alihasan, Wael A. Y. Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| description |
Over the last two decade, digital signal processing (DSP) has grown rapidly in
electronic systems to provide more reconfigureability and programmability in the
applications, compared to analog component, which allows easier design and test
automation. Digital circuit usage is increasing because of scaling properties of very
large scale integration (VLSI) processes. This has allowed new generation of digital
circuit to attain higher speed, more functionality per chip, low power dissipation,
lower cost. Analog world, analog to digital converter (ADC) are used to convert the
signal from analog to digital domain. For interfacing with DSP sample and hold
(S/H) circuit is a key building block in, and is often used in front end of the ADCs to
relax their timing requirement. The function of S/H circuit is to take samples to its
input signal and hold these samples in its output for some period of time.
The analog circuits in low voltage and low power have assumed great significance
due to mixed-mode design required for modern electronic gadgets that demand
portability and little power consumption. The mixed mode circuit has existence of
both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not
always true with analog circuits due to the constrains of device noise level and
threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same
substrate along with digital system and share same supply voltage, the operation of
analog circuit in low voltage environment is essential.
The objective of this research is to design a low-voltage, high-performance S/H
circuit that will address the above problems. A typical switch capacitor S/H circuit
needs amplifier, switches and capacitor. New amplifier have been designed by
using the architecture of single stage fully differential folded cascode low voltage
operation transconductance amplifier (OTA) which has high gain and speed; the gin
boosting technique was used for purpose of increasing the gain of the OTA. This
technique does not affect the speed of the single stage. The transmission gate
switches using CMOS devices, which have higher linearity and higher speed over a
single MOS switch, have been designed for use in the S/H circuit. The switches are
operated by clock generator with two non overlapping clock signals having low rise
and fall time offering low noise for the S/H circuit. The clock was designed with
77.17ps rise and fall time to reduce the errors of driving MOS switches which results
in higher linearity.
The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um
technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR)
65.7dB and SNR 70dB. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Alihasan, Wael A. Y. |
| author_facet |
Alihasan, Wael A. Y. |
| author_sort |
Alihasan, Wael A. Y. |
| title |
Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| title_short |
Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| title_full |
Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| title_fullStr |
Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| title_full_unstemmed |
Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology |
| title_sort |
design of low-voltage high-performance sample and hold circuit in 0.18μm cmos technology |
| granting_institution |
Universiti Putra Malaysia |
| granting_department |
Faculty of Engineering |
| publishDate |
2009 |
| url |
http://psasir.upm.edu.my/id/eprint/7357/1/FK_2009_47a.pdf |
| _version_ |
1747810692503699456 |