Software Modification in a Fault Analysis Tool for Critical Path Debugging
Microprocessor units caught with speed failure are becoming more and more eminent as the fabrication process shrinks according to Moore’s Law. Failure Analysis (FA) engineers confront the problem using Critical Path Debug method utilizing special IC (Integrated Circuit) test system capable of tes...
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| 格式: | Thesis |
| 語言: | English English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | http://psasir.upm.edu.my/id/eprint/7360/1/FK_2009_50a.pdf |
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| 總結: | Microprocessor units caught with speed failure are becoming more and more
eminent as the fabrication process shrinks according to Moore’s Law. Failure
Analysis (FA) engineers confront the problem using Critical Path Debug
method utilizing special IC (Integrated Circuit) test system capable of testing
various types of microprocessor’s failure. But such test system does not come
cheap, each costing more than USD 2.5 million. In order to bring down cost, a
system to pull test data and locate critical path using personal computer (PC) is
proposed.
This system is built upon Intel Penang’s Internal FA tool called Personal
Computer Failure Analysis (PCFA) which utilizes a host computer to collect
data from Device Under Test (DUT) through TAP (Test Access Port). As PCFA
was not originally build up to carry out critical path debug, hardware
modification and software enhancement is required. The hardware modification
involves platform rework and external FSB (Front Side Bus) frequency injection. By doing so, microprocessor speed can be controlled during test
pattern run. The software is modified to include critical-path-related test
subroutines housed inside PCFA library. These subroutines collect, compare
and display test results. The program is tested with a series of Intel’s
microprocessors to ensure that it is working as intended for current and future
products. 1000 test vector results are recorded from both PCFA and ATE’s
system to carry out compare verification.100% matched is observed for all the
test vector results thus prove the functionality of the project “Critical Path Fault
Isolation Debug for Intel Microprocessor Using Personal Computer”.
The PCFA hardware cost only USD 10 thousand which is 0.4% of the cost of an
IC test system and is currently capable of running shmoo, performing cache test,
I/O pin test and also macro Fault Isolation (FI) for each test pattern in a couple
of seconds. Although in terms of functionalities; complex IC test system will
certainly have the upper hand but in the case of solving common general
microprocessors’ failures, system based test solution is much more cost
effective. |
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